| A framework for power-gating functional units in embedded microprocessors S Roy, N Ranganathan, S Katkoori IEEE transactions on very large scale integration (VLSI) systems 17 (11 …, 2009 | 79 | 2009 |
| Run-time power-gating in caches of GPUs for leakage energy savings Y Wang, S Roy, N Ranganathan 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 300-303, 2012 | 61 | 2012 |
| State-retentive power gating of register files in multicore processors featuring multithreaded in-order cores S Roy, N Ranganathan, S Katkoori IEEE Transactions on Computers 60 (11), 1547-1560, 2010 | 40 | 2010 |
| A compiler-based leakage reduction technique by power-gating functional units in embedded microprocessors S Roy, S Katkoori, N Ranganathan 20th International Conference on VLSI Design, 215-220, 2007 | 22 | 2007 |
| Exploring compiler optimizations for enhancing power gating S Roy, N Ranganathan, S Katkoori 2009 IEEE International Symposium on Circuits and Systems, 1004-1007, 2009 | 6 | 2009 |
| Compiler-directed leakage reduction in embedded microprocessors S Roy, N Ranganathan, S Katkoori 2009 IEEE International Conference on Computer Design, 35-40, 2009 | 2 | 2009 |
| Sparse Conditional Constant Propagation in Machine SUIF S Roy, N Ranganathan, S Katkoori Website reference TBD, 2008 | 1 | 2008 |
| Architecture and compiler support for leakage reduction using power gating in microprocessors S Roy University of South Florida, 2010 | | 2010 |
| Operator Strength Reduction in Machine SUIF S Roy | | 2008 |
Nagarajan RanganathanDistinguished University Professor Emeritus of Computer Science, University of South FloridaVerified email at cse.usf.edu
