Janak H. Patel
Janak H. Patel
Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα illinois.edu
Παρατίθεται από
Παρατίθεται από
Performance of processor-memory interconnections for multiprocessors
JH Patel
IEEE Computer Architecture Letters 30 (10), 771-780, 1981
HITEC: A test generation package for sequential circuits
T Niermann, JH Patel
Proceedings of the European Conference on Design Automation., 214-218, 1991
A low-overhead coherence solution for multiprocessors with private cache memories
MS Papamarcos, JH Patel
Proceedings of the 11th annual international symposium on Computer …, 1984
Test set compaction algorithms for combinational circuits
I Hamzaoglu, JH Patel
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2000
Stride directed prefetching in scalar processors
JWC Fu, JH Patel, BL Janssens
ACM SIGMICRO Newsletter 23 (1-2), 102-110, 1992
Reducing test application time for full scan embedded cores
I Hamzaoglu, JH Patel
Digest of Papers. Twenty-Ninth Annual International Symposium on Fault …, 1999
Concurrent error detection in ALU's by recomputing with shifted operands
JH Patel, LY Fung
IEEE Trans. Computers 31 (7), 589-595, 1982
PROOFS: A fast, memory-efficient sequential circuit fault simulator
TM Niermann, WT Cheng, JH Patel
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1992
Reliability of scrubbing recovery-techniques for memory systems
AM Saleh, JJ Serrano, JH Patel
IEEE transactions on reliability 39 (1), 114-122, 1990
The effect of a multicomponent multidisciplinary bundle of interventions on sleep and delirium in medical and surgical intensive care patients
J Patel, J Baldwin, P Bunting, S Laha
Anaesthesia 69 (6), 540-549, 2014
Sequential circuit test generation in a genetic algorithm framework
EM Rudnick, JH Patel, GS Greenstein, TM Niermann
31st Design Automation Conference, 698-704, 1994
Accurate low-cost methods for performance evaluation of cache memory systems
S Laha, JH Patel, RK Iyer
IEEE Transactions on computers 37 (11), 1325-1336, 1988
Sequential circuit test generation using dynamic state traversal
MS Hsiao, EM Rudnick, JH Patel
Proceedings European Design and Test Conference. ED & TC 97, 22-28, 1997
Data prefetching in multiprocessor vector cache memories
JWC Fu, JH Patel
ACM SIGARCH Computer Architecture News 19 (3), 54-63, 1991
New techniques for deterministic test pattern generation
I Hamzaoglu, JH Patel
Journal of Electronic Testing 15 (1), 63-73, 1999
An optimization based approach to the partial scan design problem
V Chickermane, JH Patel
Proceedings. International Test Conference 1990, 377-386, 1990
A case study on the implementation of the Illinois scan architecture
FF Hsu, KM Butler, JH Patel
Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 538-547, 2001
Processor-memory interconnections for multiprocessors
JH Patel
Proceedings of the 6th Annual Symposium on Computer Architecture, 168-177, 1979
A gate-level simulation environment for alpha-particle-induced transient faults
H Cha, EM Rudnick, JH Patel, RK Iyer, GS Choi
IEEE Transactions on Computers 45 (11), 1248-1256, 1996
A fault oriented partial scan design approach
V Chickermane, JH Patel
1991 IEEE International Conference on Computer-Aided Design Digest of …, 1991
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