Ozgur Sinanoglu
Ozgur Sinanoglu
Professor of Electrical and Computer Engineering, New York University Abu Dhabi
Verified email at nyu.edu - Homepage
Title
Cited by
Cited by
Year
Security analysis of logic obfuscation
J Rajendran, Y Pino, O Sinanoglu, R Karri
Proceedings of the 49th Annual Design Automation Conference, 83-89, 2012
3512012
Security analysis of integrated circuit camouflaging
J Rajendran, M Sam, O Sinanoglu, R Karri
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications …, 2013
3252013
Fault analysis-based logic encryption
J Rajendran, H Zhang, C Zhang, GS Rose, Y Pino, O Sinanoglu, R Karri
IEEE Transactions on computers 64 (2), 410-424, 2013
2782013
SARLock: SAT attack resistant logic locking
M Yasin, B Mazumdar, JJV Rajendran, O Sinanoglu
2016 IEEE International Symposium on Hardware Oriented Security and Trust …, 2016
2172016
On improving the security of logic locking
M Yasin, JJV Rajendran, O Sinanoglu, R Karri
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
1692015
Is split manufacturing secure?
J Rajendran, O Sinanoglu, R Karri
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013
1642013
Provably-secure logic locking: From theory to practice
M Yasin, A Sengupta, MT Nabeel, M Ashraf, J Rajendran, O Sinanoglu
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications …, 2017
1402017
Logic encryption: A fault analysis perspective
J Rajendran, Y Pino, O Sinanoglu, R Karri
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 953-958, 2012
1262012
Removal attacks on logic locking and camouflaging techniques
M Yasin, B Mazumdar, O Sinanoglu, J Rajendran
IEEE Transactions on Emerging Topics in Computing, 2017
1092017
Security analysis of anti-sat
M Yasin, B Mazumdar, O Sinanoglu, J Rajendran
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 342-347, 2017
1042017
Test power reduction through minimization of scan chain transitions
O Sinanoglu, I Bayraktaroglu, A Orailoglu
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 166-171, 2002
842002
Design and analysis of ring oscillator based Design-for-Trust technique
J Rajendran, V Jyothi, O Sinanoglu, R Karri
29th VLSI Test Symposium, 105-110, 2011
832011
Sneak-path testing of crossbar-based nonvolatile random access memories
S Kannan, J Rajendran, R Karri, O Sinanoglu
IEEE Transactions on Nanotechnology 12 (3), 413-426, 2013
812013
Regaining trust in VLSI design: Design-for-trust techniques
J Rajendran, O Sinanoglu, R Karri
Proceedings of the IEEE 102 (8), 1266-1282, 2014
732014
CamoPerturb: Secure IC camouflaging for minterm protection
M Yasin, B Mazumdar, O Sinanoglu, J Rajendran
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016
642016
What to lock? Functional and parametric locking
M Yasin, A Sengupta, BC Schafer, Y Makris, O Sinanoglu, J Rajendran
Proceedings of the on Great Lakes Symposium on VLSI 2017, 351-356, 2017
612017
A novel scan architecture for power-efficient, rapid test
O Sinanoglu, A Orailoglu
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002
552002
Activation of logic encrypted chips: Pre-test or post-test?
M Yasin, SM Saeed, J Rajendran, O Sinanoglu
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 139-144, 2016
502016
Modeling scan chain modifications for scan-in test power minimization
O Sinanoglu, A Orailoglu
ITC, 602-611, 2003
492003
Scan power reduction through test data transition frequency analysis
O Sinanoglu, I Bayraktaroglu, A Orailoglu
Proceedings. International Test Conference, 844-850, 2002
482002
The system can't perform the operation now. Try again later.
Articles 1–20