Giorgos Dimitrakopoulos
Giorgos Dimitrakopoulos
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα ee.duth.gr - Αρχική σελίδα
ΤίτλοςΠαρατίθεται απόΈτος
High-speed parallel-prefix VLSI Ling adders
G Dimitrakopoulos, D Nikolos
IEEE Transactions on Computers 54 (2), 225-231, 2005
1662005
Efficient diminished-1 modulo 2/sup n/+ 1 multipliers
C Efstathiou, HT Vergos, G Dimitrakopoulos, D Nikolos
IEEE Transactions on Computers 54 (4), 491-496, 2005
762005
Fast arbiters for on-chip network switches
G Dimitrakopoulos, N Chrysos, K Galanopoulos
2008 IEEE International Conference on Computer Design, 664-670, 2008
432008
On Modulo 2^ n+ 1 Adder Design
HT Vergos, G Dimitrakopoulos
IEEE transactions on computers 61 (2), 173-186, 2010
412010
Low-power leading-zero counting and anticipation logic for high-speed floating point units
G Dimitrakopoulos, K Galanopoulos, C Mavrokefalidis, D Nikolos
IEEE transactions on very large scale integration (VLSI) systems 16 (7), 837-850, 2008
402008
Microarchitecture of Network-on-chip Routers
G Dimitrakopoulos, A Psarras, I Seitanidis
Springer, 2015
372015
New architectures for modulo 2n-1 adders
G Dimitrakopoulos, DG Nikolos, HT Vergos, D Nikolos, C Efstathiou
2005 12th IEEE International Conference on Electronics, Circuits and Systems …, 2005
332005
The fast evolving landscape of on-chip communication
D Bertozzi, G Dimitrakopoulos, J Flich, S Sonntag
Design Automation for Embedded Systems 19 (1-2), 59-76, 2015
282015
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation
A Psarras, I Seitanidis, C Nicopoulos, G Dimitrakopoulos
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
212015
Elastistore: An elastic buffer architecture for network-on-chip routers
I Seitanidis, A Psarras, G Dimitrakopoulos, C Nicopoulos
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
212014
LP-NUCA: Networks-in-cache for high-performance low-power embedded processors
DS Gracia, G Dimitrakopoulos, TM Arnal, MGH Katevenis, VV Yúfera
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (8 …, 2011
202011
A family of parallel-prefix modulo 2/sup n/-1 adders
G Dimitrakopoulos, HT Vergos, D Nikolos, C Efstathiou
Proceedings IEEE International Conference on Application-Specific Systems …, 2003
182003
A novel architecture and a systematic graph-based optimization methodology for modulo multiplication
G Dimitrakopoulos, V Paliouras
IEEE Transactions on Circuits and Systems I: Regular Papers 51 (2), 354-370, 2004
172004
ElastiNoC: A self-testable distributed VC-based network-on-chip architecture
I Seitanidis, A Psarras, E Kalligeros, C Nicopoulos, G Dimitrakopoulos
2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 135-142, 2014
142014
Merged switch allocation and traversal in network-on-chip switches
G Dimitrakopoulos, E Kalligeros, K Galanopoulos
IEEE Transactions on Computers 62 (10), 2001-2012, 2012
142012
Practical high-throughput crossbar scheduling
N Chrysos, G Dimitrakopoulos
IEEE Micro 29 (4), 22-35, 2009
132009
Sorter based permutation units for media-enhanced microprocessors
G Dimitrakopoulos, C Mavrokefalidis, K Galanopoulos, D Nikolos
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (6), 711-715, 2007
132007
ShortPath: A network-on-chip router with fine-grained pipeline bypassing
A Psarras, I Seitanidis, C Nicopoulos, G Dimitrakopoulos
IEEE Transactions on Computers 65 (10), 3136-3147, 2016
122016
Desa: Distributed elastic switch architecture for efficient networks-on-fpgas
A Roca, J Flich, G Dimitrakopoulos
22nd International Conference on Field Programmable Logic and Applications …, 2012
122012
A low-power network-on-chip architecture for tile-based chip multi-processors
A Psarras, J Lee, P Mattheakis, C Nicopoulos, G Dimitrakopoulos
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 335-340, 2016
112016
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