| An Advanced Genetic Algorithm with Improved Support Vector Machine for Multi-Class Classification of Real Power Quality Events Rahul, B Choudhary Electric Power Systems Research 191, 106879, 2020 | 25* | 2020 |
| Improved tri-state buffer in MOS current mode logic and its application N Pandey, B Choudhary Analog integrated circuits and signal processing 84, 333-340, 2015 | 11 | 2015 |
| MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells N Pandey, K Gupta, G Bhatia, B Choudhary Microelectronics journal 57, 13-20, 2016 | 9 | 2016 |
| Bus implementation using new low power PFSCL tristate buffers N Pandey, B Choudhary, K Gupta, A Mittal Active and Passive Electronic Components 2016, 2016 | 8 | 2016 |
| Design of MCML-based LFSR for low power and mixed signal applications S Agarwal, N Pandey, B Choudhary, K Gupta 2015 Annual IEEE India Conference (INDICON), 1-6, 2015 | 6 | 2015 |
| New sleep-based PFSCL tri-state inverter/buffer topologies N Pandey, B Choudhary, K Gupta, A Mittal Journal of Circuits, Systems and Computers 26 (12), 1750186, 2017 | 5 | 2017 |
| New proposal for MCML based three-input logic implementation N Pandey, K Gupta, B Choudhary VLSI Design 2016, 2016 | 5 | 2016 |
| Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style N Pandey, D Garg, K Gupta, B Choudhary Journal of Engineering 2016, 2016 | 4 | 2016 |
| Impact on DC and analog/RF performances of SOI based GaN FinFET considering high-k gate oxide VS Rajawat, A Kumar, B Choudhary Memories-Materials, Devices, Circuits and Systems 5, 100079, 2023 | 2 | 2023 |
| MCML Dynamic Register Design N Pandey, K Gupta, B Choudhary 2018 IEEE 61st International Midwest Symposium on Circuits and Systems …, 2018 | 2 | 2018 |
| Implementation of Digital Applications Using Efficient CML based designs B Choudhary 2023 International Conference on Device Intelligence, Computing and …, 2023 | 1 | 2023 |
| High-k SOI GaN FinFET for High Power and High Frequency Applications VS Rajawat, B Choudhary, A Kumar 2022 IEEE International Conference of Electron Devices Society Kolkata …, 2022 | 1 | 2022 |
| Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications A Kumar, N Gupta, A Jain, R Gupta, B Choudhary, K Kumar, AK Goyal, ... Memories-Materials, Devices, Circuits and Systems 6, 100087, 2023 | | 2023 |
| Optimization in PFSCL Design Using Floating-Gate MOSFET R Bhaskar, B Choudhary, R Saha 2023 Second International Conference on Trends in Electrical, Electronics …, 2023 | | 2023 |
| Machine Learning and Deep Learning Based Hybrid Approach for Power Quality Disturbances Analysis R Rahul, B Choudhary 2023 International Conference on Computational Intelligence and Knowledge …, 2023 | | 2023 |
| Implementation of Half Adder Using Recessed Channel MOSFET Based on Mixed-Mode Simulation B CHOUDHARY | | 2016 |
| New design of Exclusive-OR (EX-OR) gate by using low-power MCML tri-state buffer B Choudhary International Journal of Electronics, Electrical and Computational System 4 …, 2015 | | 2015 |
Neeta PandeyDelhi Technological University DelhiVerified email at dce.ac.in
