| BDS: A BDD-based logic optimization system C Yang, M Ciesielski, V Singhal Proceedings of the 37th Annual Design Automation Conference, 92-97, 2000 | 345 | 2000 |
| Wave-pipelining: A tutorial and research survey WP Burleson, M Ciesielski, F Klass, W Liu IEEE Transactions on very large scale integration (vlsi) systems 6 (3), 464-474, 1998 | 339 | 1998 |
| Logic synthesis and verification S Hassoun, T Sasao Springer Science & Business Media, 2001 | 222 | 2001 |
| Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization S Yang, MJ Ciesielski Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1991 | 125 | 1991 |
| LPSAT: a unified approach to RTL satisfiability Z Zeng, P Kalla, M Ciesielski Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001 | 118 | 2001 |
| Verification of gate-level arithmetic circuits by function extraction M Ciesielski, C Yu, W Brown, D Liu, A Rossi Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 85 | 2015 |
| Taylor expansion diagrams: A canonical representation for verification of data flow designs M Ciesielski, P Kalla, S Askar IEEE Transactions on Computers 55 (9), 1188-1201, 2006 | 84 | 2006 |
| Taylor expansion diagrams: A compact, canonical representation with applications to symbolic verification MJ Ciesielski, P Kalla, Z Zheng, B Rouzeyre Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 84 | 2002 |
| Incremental SAT-based reverse engineering of camouflaged logic circuits C Yu, X Zhang, D Liu, M Ciesielski, D Holcomb IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 81 | 2017 |
| PLADE: A two-stage PLA decomposition MJ Ciesielski, S Yang Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1992 | 73 | 1992 |
| Expression of HER2 in colorectal cancer does not correlate with prognosis WJ Kruszewski, R Rzepko, M Ciesielski, J Szefel, J Zieliński, M Szajewski, ... Disease markers 29 (5), 207-212, 2010 | 69 | 2010 |
| Formal verification of arithmetic circuits by function extraction C Yu, W Brown, D Liu, A Rossi, M Ciesielski IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 64 | 2016 |
| Fast algebraic rewriting based on and-inverter graphs C Yu, M Ciesielski, A Mishchenko IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 60 | 2017 |
| Clock period minimization with wave pipelining DA Joy, MJ Ciesielski IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993 | 55 | 1993 |
| BDD decomposition for efficient logic synthesis C Yang, V Singhal, M Ciesielski Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999 | 53 | 1999 |
| An optimum layer assignment for routing in ICs and PCBs MJ Ciesielski, E Kinnen 18th Design Automation Conference, 733-737, 1981 | 51 | 1981 |
| Multiple-valued Boolean minimization based on graph coloring MJ Ciesielski, S Yang, MA Perkowski Proceedings 1989 IEEE International Conference on Computer Design: VLSI in …, 1989 | 48 | 1989 |
| Understanding algebraic rewriting for arithmetic circuit verification: a bit-flow model M Ciesielski, T Su, A Yasin, C Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 47 | 2019 |
| Functional test generation using constraint logic programming Z Zeng, MJ Ciesielski, B Rouzeyre 11th International Conference on VLSI/SOC, 375-387, 2002 | 47 | 2002 |
| Practical design verification DK Pradhan, IG Harris Cambridge University Press, 2009 | 39 | 2009 |
E. BoutillonLab-STICC, Université de Bretagne SudVerified email at univ-ubs.fr
