| Speed comparison of 16x16 vedic multipliers M Pradhan, R Panda, SK Sahu International journal of computer applications 21 (6), 0975-8887, 2011 | 58 | 2011 |
| FPGA implementation of RSA encryption system SK Sahu, M Pradhan International Journal of Computer Applications 19 (9), 10-12, 2011 | 30 | 2011 |
| Design and implementation of vedic multiplier M Pradhan, R Panda AMSE Journal, Series D, Computer Science and Statistics, France 15 (2), 1-19, 2010 | 27 | 2010 |
| High speed multiplier using Nikhilam Sutra algorithm of Vedic mathematics M Pradhan, R Panda International Journal of Electronics 101 (3), 300-307, 2014 | 24 | 2014 |
| Time efficient signed Vedic multiplier using redundant binary representation RK Barik, M Pradhan, R Panda The Journal of Engineering 2017 (3), 60-68, 2017 | 23 | 2017 |
| Design and evaluation of an efficient parity-preserving reversible QCA gate with online testability B Bhoi, NK Misra, M Pradhan Cogent Engineering 4 (1), 1416888, 2017 | 21 | 2017 |
| Efficient ASIC and FPGA implementation of cube architecture RK Barik, M Pradhan IET computers & digital techniques 11 (1), 43-49, 2017 | 19 | 2017 |
| MAC implementation using vedic multiplication algorithm M Pradhan, R Panda, SK Sahu International journal of computer applications 21 (7), 26-28, 2011 | 18 | 2011 |
| Novel robust design for reversible code converters and binary incrementer with quantum-dot cellular automata BK Bhoi, NK Misra, M Pradhan Intelligent Computing and Information and Communication: Proceedings of 2nd …, 2018 | 17 | 2018 |
| Implementation of Modular multiplication for RSA Algorithm SK Sahu, M Pradhan 2011 International Conference on Communication Systems and Network …, 2011 | 17 | 2011 |
| Novel binary divider architecture for high speed VLSI applications R Senapati, BK Bhoi, M Pradhan 2013 IEEE Conference on Information & Communication Technologies, 675-679, 2013 | 15 | 2013 |
| Fast signed multiplier using Vedic Nikhilam algorithm SR Sahu, BK Bhoi, M Pradhan IET Circuits, Devices & Systems 14 (8), 1160-1166, 2020 | 14 | 2020 |
| Area-time efficient square architecture RK Barik, M Pradhan AMSE J., Adv. D 20 (1), 21-34, 2015 | 12 | 2015 |
| Synthesis comparison of Karatsuba multiplierusing polynomial multiplication, vedic multiplier and classical multiplier S Mishra, M Pradhan International journal of computer applications 41 (9), 13-17, 2012 | 12 | 2012 |
| Implementation of karatsuba algorithm using polynomial multiplication S Mishra, M Pradhan Indian Journal of Computer Science and Engineering, ISSN 976 (5166), 88-93, 2012 | 11 | 2012 |
| Efficient conversion technique from redundant binary to nonredundant binary representation RK Barik, M Pradhan, R Panda Journal of Circuits, Systems and Computers 26 (09), 1750135, 2017 | 9 | 2017 |
| Design of magnetic dipole based 3D integration nano-circuits for future electronics application BK Bhoi, NK Misra, M Pradhan International Journal of Nano Dimension 9 (4), 374-385, 2018 | 7 | 2018 |
| A universal reversible gate architecture for designing n-bit comparator structure in quantum-dot cellular automata BK Bhoi, NK Misra, M Pradhan International Journal of Grid and Distributed Computing 10 (9), 33-46, 2017 | 7 | 2017 |
| Efficient hardware realization of signed arithmetic operation using IEN RK Barik, I Samal, M Pradhan 2015 IEEE Power, Communication and Information Technology Conference (PCITC …, 2015 | 6 | 2015 |
| An efficient redundant binary adder with revised computational rules RK Barik, BK Bhoi, M Pradhan Computers & Electrical Engineering 72, 224-236, 2018 | 5 | 2018 |
Dr. Bandan Kumar BhoiVerified email at vssut.ac.in
