Wladyslaw Grabinski
Wladyslaw Grabinski
GMC Suisse, MOS-AK, EPFL, ETHZ
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα grabinski.ch - Αρχική σελίδα
Τίτλος
Παρατίθεται από
Παρατίθεται από
Έτος
RF distortion analysis with compact MOSFET models
P Bendix, P Rakers, P Wagh, L Lemaitre, W Grabinski, CC McAndrew, ...
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat …, 2004
722004
TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model
A Biswas, SS Dan, C Le Royer, W Grabinski, AM Ionescu
Microelectronic Engineering 98, 334-337, 2012
572012
Transistor level modeling for analog/RF IC design
W Grabinski, B Nauwelaers, D Schreurs
Springer, 2006
512006
An adjusted constant-current method to determine saturated and linear mode threshold voltage of MOSFETs
A Bazigos, M Bucher, J Assenmacher, S Decker, W Grabinski, ...
IEEE Transactions on Electron Devices 58 (11), 3751-3758, 2011
442011
Electrical modeling of a pressure sensor MOSFET
JM Sallese, W Grabinski, V Meyer, C Bassin, P Fazan
Sensors and Actuators A: Physical 94 (1-2), 53-58, 2001
392001
Investigation of tunnel field-effect transistors as a capacitor-less memory cell
A Biswas, N Dagtekin, W Grabinski, A Bazigos, C Le Royer, JM Hartmann, ...
Applied Physics Letters 104 (9), 092108, 2014
372014
Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model
C Lallement, JM Sallese, M Bucher, W Grabinski, PC Fazan
IEEE Transactions on Electron Devices 50 (2), 406-417, 2003
322003
EKV3. 0: An advanced charge based MOS transistor model. A design-oriented MOS transistor compact model
M Bucher, A Bazigos, F Krummenacher, JM Sallese, C Enz
Transistor Level Modeling for Analog/RF IC Design, 67-95, 2006
222006
Compact device modeling using Verilog-AMS and ADMS
L Lemaitre, W Grabiński, C McAndrew
Electron Technology: Internet Journal 35 (3), 1-5, 2003
172003
Steep slope VO2switches for wide-band (DC-40 GHz) reconfigurable electronics
WA Vitale, A Paone, M Fernández-Bolaños, A Bazigos, W Grabinski, ...
72nd Device Research Conference, 29-30, 2014
162014
Accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain
M Najmzadeh, D Bouvet, W Grabinski, JM Sallese, AM Ionescu
Solid-state electronics 74, 114-120, 2012
162012
Power/HVMOS Devices Compact Modeling
W Grabinski, T Gneiting
Springer Verlag, 2010
142010
Extended charges modeling for deep submicron CMOS
M Bucher, JM Sallese, C Lallement, W Grabinski, CC Enz, ...
Int. Semicond. Device Research Symp.(ISDRS’99), 397-400, 1999
141999
Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm
M Najmzadeh, M Berthomé, JM Sallese, W Grabinski, AM Ionescu
Solid-state electronics 98, 55-62, 2014
132014
Compact modelling of ultra deep submicron CMOS devices
W GRABIŃSKI, JM SALLESE, M BUCHER, F KRUMMENACHER
TECHNICAL, SCIENCES 50 (1), 2002
132002
Advancements in DC and RF Mosfet modeling with the EPFL-EKV charge based model
JM Sallese, W Grabinski, AS Porret, M Bucher, C Lallement, ...
8th Int. Conf. MIXDES, 45-52, 2001
122001
Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs
M Najmzadeh, JM Sallese, M Berthomé, W Grabinski, AM Ionescu
IEEE transactions on electron devices 59 (12), 3519-3526, 2012
112012
Process control monitor based extraction procedure for statistical compact MOSFET modeling
M Yakupov, D Tomaszewski, W Grabinski
Proceedings of the 17th International Conference Mixed Design of Integrated …, 2010
102010
A versatile setup for semiconductor testing up to 550° C
W Grabinski, A Stricker, W Fichtner
101998
Multigate buckled self-aligned dual Si nanowire MOSFETs on bulk Si for high electron mobility
M Najmzadeh, Y Tsuchiya, D Bouvet, W Grabinski, AM Ionescu
IEEE transactions on nanotechnology 11 (5), 902-906, 2012
92012
Δεν είναι δυνατή η εκτέλεση της ενέργειας από το σύστημα αυτή τη στιγμή. Προσπαθήστε ξανά αργότερα.
Άρθρα 1–20