Joseph Hassoun
Joseph Hassoun
Samsung Semiconductor Inc.
Verified email at samsung.com - Homepage
Title
Cited by
Cited by
Year
Delay lock loop with clock phase shifter
JH Hassoun, FE Goetting, JD Logue
US Patent 6,289,068, 2001
1402001
Programmable logic core adapter
JM Arnold, RC Camarota, JH Hassoun, R Charle'R
US Patent 6,744,274, 2004
782004
SDRAM controller implemented in a PLD
JH Hassoun
US Patent 6,487,648, 2002
712002
Precision trim circuit for delay lines
FE Goetting, PG Hyland, JH Hassoun
US Patent 6,204,710, 2001
562001
Delay lock loop with clock phase shifter
JH Hassoun, FE Goetting, JD Logue
US Patent 6,587,534, 2003
482003
Cache tag system for use with multiple processors including the most recently requested processor identification
JH Hassoun, ML Ziegler, RD Odineal
US Patent 5,737,757, 1998
411998
Double data rate flip-flop
SP Young, SM Menon, K Sodha, RA Carberry, JH Hassoun
US Patent 6,525,565, 2003
382003
Variable clock divider with selectable duty cycle
JH Hassoun
US Patent 6,061,418, 2000
342000
Current mode interface circuitry for an IC test device
JH Hassoun, JA Gasbarro
US Patent 5,844,913, 1998
311998
Forming linked lists using content addressable memory
S Iacobovici, WR Bryg, JH Hassoun
US Patent 5,995,967, 1999
291999
An elemental computing architecture for SD radio
S Kelem, B Box, S Wasson, R Plunkett, J Hassoun, C Phillips
Proc. Software Defined Radio Technical Conf. Product Exposition, 2007
222007
Double data rate flip-flop
SP Young, SM Menon, K Sodha, RA Carberry, JH Hassoun
US Patent 6,777,980, 2004
202004
Post-training piecewise linear quantization for deep neural networks
J Fang, A Shafiee, H Abdel-Aziz, D Thorsley, G Georgiadis, JH Hassoun
European Conference on Computer Vision, 69-86, 2020
172020
Forming linked lists using content addressable memory
S Iacobovici, WR Bryg, JH Hassoun
US Patent 6,820,086, 2004
122004
Double data rate flip-flop
SP Young, SM Menon, K Sodha, RA Carberry, JH Hassoun
US Patent 7,317,773, 2008
102008
Near-lossless post-training quantization of deep neural networks via a piecewise linear approximation
J Fang, A Shafiee, H Abdel-Aziz, D Thorsley, G Georgiadis, J Hassoun
arXiv preprint arXiv:2002.00104, 4, 2020
62020
Efficient computer terminal system utilizing a single slave processor
JH Hassoun
US Patent 5,148,516, 1992
41992
Neural processor
I Ovsiannikov, AS Ardestani, JH Hassoun, L Wang, SH Lee, S Joonho, ...
US Patent App. 16/446,610, 2019
32019
Sparsity-Aware and Re-configurable NPU Architecture for Samsung Flagship Mobile SoC
JW Jang, S Lee, D Kim, H Park, AS Ardestani, Y Choi, C Kim, Y Kim, H Yu, ...
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
22021
Learned token pruning for transformers
S Kim, S Shen, D Thorsley, A Gholami, J Hassoun, K Keutzer
arXiv preprint arXiv:2107.00910, 2021
12021
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