Masato Edahiro
Masato Edahiro
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Cited by
Cited by
A clustering-based optimization algorithm in zero-skew routings
M Edahiro
Proceedings of the 30th international Design Automation Conference, 612-616, 1993
Practical use of bucketing techniques in computational geometry
T Asano, M Edahiro, I Hiroshi, IRI Masao, K Murota
Machine Intelligence and Pattern Recognition 2, 153-195, 1985
Information communication device and program execution environment control method
H Inoue, J Sakai, T Abe, M Edahiro
US Patent 8,640,194, 2014
Data transfer matters for GPU computing
Y Fujii, T Azumi, N Nishio, S Kato, M Edahiro
2013 International Conference on Parallel and Distributed Systems, 275-282, 2013
A 600MIPS 120mW 70/spl mu/A leakage triple-CPU mobile application processor chip
S Torii, S Suzuki, H Tomonaga, T Tokue, J Sakai, N Suzuki, K Murakami, ...
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005
Delay minimization for zero-skew routing
M Edahiro
IEEE International Conference on Computer Aided Design, 563-563, 1993
Information processing device comprising a plurality of domains having a plurality of processors, recovery device, program and recovery method
H Inoue, J Sakai, T Abe, M Uekubo, N Suzuki, M Edahiro
US Patent 8,365,021, 2013
An efficient zero-skew routing algorithm
M Edahiro
Proceedings of the 31st annual Design Automation Conference, 375-380, 1994
Multiple processor system, system structuring method in multiple processor system and program thereof
H Inoue, J Sakai, T Abe, M Edahiro
US Patent App. 12/447,513, 2010
Minimum skew and minimum path length routing in VLSI layout design
M Edahiro
NEC research & development 32 (4), 569-575, 1991
Power and performance characterization and modeling of GPU-accelerated systems
Y Abe, H Sasaki, S Kato, K Inoue, M Edahiro, M Peres
2014 IEEE 28th international parallel and distributed processing symposium …, 2014
Laser beam machining apparatus
Y Onoma, M Edahiro
US Patent 6,239,406, 2001
A 1 GIPS 1 W single-chip tightly-coupled four-way multiprocessor with architecture support for multiple control flow execution
N Nishi, T Inoue, M Nomura, S Matsushita, S Torii, A Shibayama, J Sakai, ...
2000 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2000
A single-chip multiprocessor for smart terminals
M Edahiro, S Matsushita, M Yamashina, N Nishi
IEEE Micro 20 (04), 12-20, 2000
Minimum path-length equi-distant routing
M Edahiro
Proc. APCCAS 92, 1992
Interconnect design strategy: structures, repeaters and materials with strategic system performance analysis (S/sup 2/PAL) model
S Takahashi, M Edahiro, Y Hayashi
IEEE Transactions on Electron Devices 48 (2), 239-251, 2001
New placement and global routing algorithms for standard cell layouts
M Edahiro, T Yoshimura
27th ACM/IEEE Design Automation Conference, 642-645, 1990
GPU implementations of object detection using HOG features and deformable models
M Hirabayashi, S Kato, M Edahiro, K Takeda, T Kawano, S Mita
2013 IEEE 1st International Conference on Cyber-Physical Systems, Networks …, 2013
Parallelizing fundamental algorithms such as sorting on multi-core processors for EDA acceleration
M Edahiro
2009 Asia and South Pacific Design Automation Conference, 230-233, 2009
Comparison of preemption schemes for partially reconfigurable FPGAs
K Jozwik, H Tomiyama, M Edahiro, S Honda, H Takada
IEEE Embedded Systems Letters 4 (2), 45-48, 2012
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