Dr. Manish Kumar Jaiswal
Dr. Manish Kumar Jaiswal
Huawei Technology, Hong Kong
Verified email at - Homepage
Cited by
Cited by
Z-TCAM: An SRAM-based Architecture for TCAM
Z Ullah, MK Jaiswal, RCC Cheung
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (2), 402-406, 2015
PACoGen: A Hardware Posit Arithmetic Core Generator
MK Jaiswal, HKH So
IEEE Access 7, 74586 - 74601, 2019
FPGA Based High Performance and Scalable Block LU Decomposition Architecture
MK Jaiswal, N Chandrachoodan
Computers, IEEE Transactions on 61 (1), 60-72, 2012
E-TCAM: An Efficient SRAM-Based Architecture for TCAM
Z Ullah, MK Jaiswal, RCC Cheung
Circuits, Systems, and Signal Processing 33 (5), 1-22, 2014
UE-TCAM: an ultra efficient SRAM-based TCAM
Z Ullah, MK Jaiswal, RCC Cheung, HKH So
TENCON 2015-2015 IEEE Region 10 Conference, 1-6, 2015
Universal number posit arithmetic generator on FPGA
MK Jaiswal, HKH So
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
Architecture generator for type-3 unum posit adder/subtractor
MK Jaiswal, HKH So
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
FPGA Implementation of SRAM-based Ternary Content Addressable Memory
Z Ullah, MK Jaiswal, YC Chan, RCC Cheung
The IEEE 26th International Parallel and Distributed Processing Symposium …, 2012
Fast content updating algorithm for an SRAM-based TCAM on FPGA
F Syed, Z Ullah, MK Jaiswal
IEEE Embedded Systems Letters 10 (3), 73-76, 2017
Unified architecture for double/two-parallel single precision floating point adder
MK Jaiswal, RCC Cheung, M Balakrishnan, K Paul
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (7), 521-525, 2014
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support
MK Jaiswal, RCC Cheung
Microelectronics journal 44 (5), 421-430, 2013
High Performance FPGA Implementation of Double Precision Floating Point Adder/Subtractor
MK Jaiswal, RCC Cheung
International Journal of Hybrid Information Technology 4 (4), 71-8-, 2011
DSP48E efficient floating point multiplier architectures on FPGA
MK Jaiswal, HKH So
30th International Conference on VLSI Design and 2017 16th International …, 2017
VLSI implementation of double-precision floating-point multiplier using karatsuba technique
MK Jaiswal, RCC Cheung
Circuits, systems, and signal processing 32, 15-27, 2013
Area-efficient architectures for large integer and quadruple precision floating point multipliers
MK Jaiswal, RCC Cheung
2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division
MK Jaiswal, HKH So
IEEE TCAS1 64 (02), 386-398, 2017
Dual-mode double precision/two-parallel single precision floating point multiplier architecture
MK Jaiswal, HKH So
2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015
Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA
MK Jaiswal, N Chandrachoodan
Industrial and Information Systems, 2008. ICIIS 2008. IEEE Region 10 and the …, 2008
Configurable Architectures for Multi-Mode Floating Point Adders
MK Jaiswal, BSC Varma, HKH So, M Balakrishnan, K Paul, RCC Cheung
Circuits and Systems I: Regular Papers, IEEE Transactions on 62 (8), 2079-2090, 2015
Series Expansion based Efficient Architectures for Double Precision Floating Point Division
MK Jaiswal, RCC Cheung, M Balakrishnan, K Paul
Circuits, Systems, and Signal Processing 33 (5), 1-28, 2014
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