Παρακολούθηση
Pavlos Mattheakis
Pavlos Mattheakis
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα synopsys.com - Αρχική σελίδα
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Παρατίθεται από
Παρατίθεται από
Έτος
Clock tree resynthesis for multi-corner multi-mode timing closure
S Roy, PM Mattheakis, L Masse-Navette, DZ Pan
Proceedings of the 2014 on International symposium on physical design, 69-76, 2014
472014
A low-power network-on-chip architecture for tile-based chip multi-processors
A Psarras, J Lee, P Mattheakis, C Nicopoulos, G Dimitrakopoulos
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 335-340, 2016
222016
Timing-driven and placement-aware multibit register composition
I Seitanidis, G Dimitrakopoulos, PM Mattheakis, L Masse-Navette, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
122018
Significantly reducing MPI intercommunication latency and power overhead in both embedded and HPC systems
PM Mattheakis, I Papaefstathiou
ACM Transactions on Architecture and Code Optimization (TACO) 9 (4), 1-25, 2013
112013
Evolving challenges and techniques for nanometer SoC clock network synthesis
S Roy, PM Mattheakis, L Masse-Navette, DZ Pan
2014 12th IEEE International Conference on Solid-State and Integrated …, 2014
82014
Hardware primitives for the synthesis of multithreaded elastic systems
G Dimitrakopoulos, I Seitanidis, A Psarras, K Tsiouris, PM Mattheakis, ...
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
62014
Asynchronous, multi-rail digital circuit with gating and gated sub-circuits and method for designing the same
CP Sotiriou, P Mattheakis
US Patent 7,603,635, 2009
62009
Timing driven incremental multi-bit register composition using a placement-aware ILP formulation
I Seitanidis, G Dimitrakopoulos, P Mattheakis, L Masse-Navete, ...
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
52017
A polynomial time flow for implementing free-choice Petri-nets
PM Mattheakis, CP Sotiriou, PA Beerel
2012 IEEE 30th International Conference on Computer Design (ICCD), 227-234, 2012
52012
Skew bounded buffer tree resynthesis for clock power optimization
S Roy, DZ Pan, PM Mattheakis, PS Colyer, L Masse-Navette, PO Ribet
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 87-90, 2015
42015
Polynomial complexity asynchronous control circuit synthesis of concurrent specifications based on burst-mode FSM decomposition
PM Mattheakis, CP Sotiriou
2013 26th International Conference on VLSI Design and 2013 12th …, 2013
32013
Logic synthesis of concurrent controller specifications
PM Mattheakis
Ph. D. dissertation, 2013
32013
Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV
D Mangiras, P Mattheakis, PO Ribet, G Dimitrakopoulos
Proceedings of the 2020 International Symposium on Physical Design, 25-32, 2020
22020
Accelerating intercommunication in highly parallel systems
N Tampouratzis, PM Mattheakis, I Papaefstathiou
ACM Transactions on Architecture and Code Optimization (TACO) 13 (4), 1-25, 2016
12016
Actual-delay circuits on FPGA: Trading-off luts for speed
E Kassapaki, PM Mattheakis, CP Sotiriou
2006 International Conference on Field Programmable Logic and Applications, 1-6, 2006
12006
Apparatus and method for mixed single-rail and dual-rail combinational logic with completion detection
CP Sotiriou, P Mattheakis, M Christofilopoulos
US Patent 8,074,193, 2011
2011
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