Omer Khan
Cited by
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Crono: A benchmark suite for multithreaded graph algorithms executing on futuristic multicores
M Ahmad, F Hijaz, Q Shi, O Khan
2015 IEEE International Symposium on Workload Characterization, 44-55, 2015
Suppressing the oblivious ram timing channel while making information leakage and program efficiency trade-offs
CW Fletcher, L Ren, X Yu, M Van Dijk, O Khan, S Devadas
High Performance Computer Architecture (HPCA), 2014 IEEE 20th International …, 2014
Scalable, accurate multicore simulation in the 1000-core era
M Lis, P Ren, MH Cho, KS Shim, CW Fletcher, O Khan, S Devadas
(IEEE ISPASS) IEEE International Symposium on Performance Analysis of …, 2011
DARSIM: a parallel cycle-level NoC simulator
M Lis, KS Shim, MH Cho, P Ren, O Khan, S Devadas
Hornet: A cycle-level multicore simulator
P Ren, M Lis, MH Cho, KS Shim, CW Fletcher, O Khan, N Zheng, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
A self-adaptive system architecture to address transistor aging
O Khan, S Kundu
2009 Design, Automation & Test in Europe Conference & Exhibition, 81-86, 2009
Advancing the state-of-the-art in hardware trojans detection
SK Haider, C Jin, M Ahmad, DM Shila, O Khan, M van Dijk
IEEE Transactions on Dependable and Secure Computing 16 (1), 18-32, 2017
The locality-aware adaptive cache coherence protocol
G Kurian, O Khan, S Devadas
Proceedings of the 40th Annual International Symposium on Computer …, 2013
Performance per watt benefits of dynamic core morphing in asymmetric multicores
R Rodrigues, A Annamalai, I Koren, S Kundu, O Khan
2011 International conference on parallel architectures and compilation …, 2011
Locality-aware data replication in the last-level cache
G Kurian, S Devadas, O Khan
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
A self-adaptive scheduler for asymmetric multi-cores
O Khan, S Kundu
Proceedings of the 20th symposium on Great lakes symposium on VLSI, 397-400, 2010
IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications
H Omar, O Khan
2020 IEEE International Symposium on High Performance Computer Architecture …, 2020
The execution migration machine: Directoryless shared-memory architecture
KS Shim, M Lis, O Khan, S Devadas
Computer 48 (9), 50-59, 2015
A cross-layer multicore architecture to tradeoff program accuracy and resilience overheads
Q Shi, H Hoffmann, O Khan
IEEE Computer Architecture Letters 14 (2), 85-89, 2014
Thread relocation: A runtime architecture for tolerating hard errors in chip multiprocessors
O Khan, S Kundu
IEEE Transactions on Computers 59 (5), 651-665, 2009
Time-predictable computer architecture for cyber-physical systems: Digital emulation of power electronics systems
M Kinsy, O Khan, I Celanovic, D Majstorovic, N Celanovic, S Devadas
2011 IEEE 32nd Real-Time Systems Symposium, 305-316, 2011
Execution migration
S Devadas, O Khan, M Lis, KS Shim, MH Cho
US Patent 8,904,154, 2014
Memory coherence in the age of multicores
M Lis, KS Shim, MH Cho, S Devadas
2011 IEEE 29th International Conference on Computer Design (ICCD), 1-8, 2011
Deadlock-free fine-grained thread migration
MH Cho, KS Shim, M Lis, O Khan, S Devadas
Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on …, 2011
Towards sparsification of graph neural networks
H Peng, D Gurevin, S Huang, T Geng, W Jiang, O Khan, C Ding
2022 IEEE 40th International Conference on Computer Design (ICCD), 272-279, 2022
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