| Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description L Charvát, A Smrčka, T Vojnar Proceedings of the 13th International Workshop on Microprocessor Test and …, 2012 | 10 | 2012 |
| HADES: Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems L Charvát, A Smrčka, T Vojnar arXiv preprint arXiv:1612.04986, 2016 | 6 | 2016 |
| Using Formal Verification of Parameterized Systems in RAW Hazard Analysis In Microprocessors L Charvát, A Smrčka, T Vojnar Microprocessor Test and Verification Workshop (MTV), 2014 15th International …, 2014 | 6 | 2014 |
| An Abstraction of Multi-Port Memories with Arbitrary Addressable Units L Charvát, A Smrčka, T Vojnar Computer Aided Systems Theory-EUROCAST 2013, 460-468, 2013 | 4 | 2013 |
| An Abstraction of Multi-Port Memories with Arbitrary Addressable Units L Charvát, A Smrčka, T Vojnar Proceedings of the 14th Computer Aided Systems Theory, 254-255, 2013 | 4 | 2013 |
| Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems L Charvát, A Smrčka, T Vojnar Proceedings of the 15th International Conference on Computer Aided Systems …, 2015 | 3 | 2015 |
| Utilizing parametric systems for detection of pipeline hazards L Charvát, A Smrčka, T Vojnar International Journal on Software Tools for Technology Transfer, 1-28, 2020 | | 2020 |
| Automated Verification in HW/SW Co-design L Charvát Brno University of Technology, 2020 | | 2020 |
