| A new stochastic computing methodology for efficient neural network implementation V Canals, A Morro, A Oliver, ML Alomar, JL Rosselló IEEE Transactions on Neural Networks and Learning Systems 27 (3), 551-564, 2016 | 115 | 2016 |
| A variable threshold voltage inverter for CMOS programmable logic circuits J Segura, JL Rossello, J Morra, H Sigg IEEE Journal of Solid-State Circuits 33 (8), 1262-1265, 1998 | 64 | 1998 |
| Studying the role of synchronized and chaotic spiking neural ensembles in neural information processing JL Rossello, V Canals, A Oliver, A Morro International journal of neural systems 24 (05), 1430003, 2014 | 58 | 2014 |
| An analytical charge-based compact delay model for submicrometer CMOS inverters JL Rosselló, J Segura IEEE Transactions on Circuits and Systems I: Regular Papers 51 (7), 1301-1311, 2004 | 58 | 2004 |
| A Stochastic Spiking Neural Network for Virtual Screening A Morro, V Canals, A Oliver, ML Alomar, F Galán-Prado, PJ Ballester, ... IEEE Transactions on Neural Networks and Learning Systems 29 (4), 1371 - 1375, 2018 | 53 | 2018 |
| FPGA-based stochastic echo state networks for time-series forecasting ML Alomar, V Canals, N Perez-Mora, V Martínez-Moll, JL Rosselló Computational intelligence and neuroscience 2016, 15-15, 2016 | 50 | 2016 |
| Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers JL Rosselló, J Segura IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002 | 46 | 2002 |
| Hardware implementation of stochastic spiking neural networks JL Rossello, V Canals, A Morro, A Oliver International journal of neural systems 22 (04), 1250014, 2012 | 42 | 2012 |
| Digital implementation of a single dynamical node reservoir computer ML Alomar, MC Soriano, M Escalona-Morán, V Canals, I Fischer, ... IEEE Transactions on Circuits and Systems II: Express Briefs 62 (10), 977-981, 2015 | 36 | 2015 |
| Ultra-fast data-mining hardware architecture based on stochastic computing A Morro, V Canals, A Oliver, ML Alomar, JL Rossello PloS one 10 (5), e0124176, 2015 | 36 | 2015 |
| Chaos-based mixed signal implementation of spiking neurons JL Rossello, V Canals, A Morro, J Verd International Journal of Neural Systems 19 (06), 465-471, 2009 | 36 | 2009 |
| Impact of thermal gradients on clock skew and testing SA Bota, JL Rossello, C De Benito, A Keshavarzi, J Segura IEEE Design & Test of Computers 23 (5), 414-424, 2006 | 34 | 2006 |
| Hardware implementation of stochastic-based neural networks JL Rosselló, V Canals, A Morro The 2010 International Joint Conference on Neural Networks (IJCNN), 1-4, 2010 | 28 | 2010 |
| High-density liquid-state machine circuitry for time-series forecasting JL Rosselló, ML Alomar, A Morro, A Oliver, V Canals International journal of neural systems 26 (05), 1550036, 2016 | 27 | 2016 |
| A compact gate-level energy and delay model of dynamic CMOS gates JL Rosselló, C de Benito, J Segura IEEE Transactions on Circuits and Systems II: Express Briefs 52 (10), 685-689, 2005 | 27 | 2005 |
| A simple CMOS chaotic integrated circuit JL Rosselló, V Canals, I De Paul, S Bota, A Morro IEICE Electronics Express 5 (24), 1042-1048, 2008 | 26 | 2008 |
| Smart temperature sensor for thermal testing of cell-based ICs SA Bota, M Rosales, JL Rosselló, J Segura Design, Automation and Test in Europe, 464-465, 2005 | 26 | 2005 |
| Within die thermal gradient impact on clock-skew: a new type of delay-fault mechanism S Bota, M Rosales, JL Rosselló, J Segura International Test Conference 2004, 2004 | 26 | 2004 |
| Energy-efficient pattern recognition hardware with elementary cellular automata A Moran, CF Frasser, M Roca, JL Rossello IEEE Transactions on Computers 69 (3), 392-401, 2019 | 25* | 2019 |
| Probabilistic-based neural network implementation JL Rosselló, V Canals, A Morro The 2012 International Joint Conference on Neural Networks (IJCNN), 1-7, 2012 | 24 | 2012 |
Vincent CanalsAssociate Professor,Industrial Eng. Dept. , University of Balearic IslandsVerified email at uib.es
