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Matthew Mattina
Matthew Mattina
Unknown affiliation
Verified email at alumni.princeton.edu
Title
Cited by
Cited by
Year
On-chip interconnection architecture of the tile processor
D Wentzlaff, P Griffin, H Hoffmann, L Bao, B Edwards, C Ramey, ...
IEEE micro 27 (5), 15-31, 2007
11252007
Tile64-processor: A 64-core soc with mesh interconnect
S Bell, B Edwards, J Amann, R Conlin, K Joyce, V Leung, J MacKay, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
8212008
Computing in parallel processing environments
PR Griffin, M Hostetter, A Agarwal, CC Miao, CD Metcalf, B Edwards, ...
US Patent 8,738,860, 2014
2682014
Scale-sim: Systolic cnn accelerator simulator
A Samajdar, Y Zhu, P Whatmough, M Mattina, T Krishna
arXiv preprint arXiv:1811.02883, 2018
1982018
Last level cache (llc) performance of data mining workloads on a cmp-a case study of parallel bioinformatics workloads
A Jaleel, M Mattina, B Jacob
The Twelfth International Symposium on High-Performance Computer …, 2006
1752006
Tarantula: A vector extension to the alpha architecture
R Espasa, F Ardanaz, J Emer, S Felix, J Gago, R Gramunt, I Hernandez, ...
Proceedings 29th Annual International Symposium on Computer Architecture …, 2002
1382002
Caching in multicore and multiprocessor architectures
A Agarwal, IR Bratt, M Mattina
US Patent 7,805,575, 2010
812010
Sparse: Sparse architecture search for cnns on resource-constrained microcontrollers
I Fedorov, RP Adams, M Mattina, P Whatmough
Advances in Neural Information Processing Systems 32, 2019
782019
Micronets: Neural network architectures for deploying tinyml applications on commodity microcontrollers
C Banbury, C Zhou, I Fedorov, R Matas, U Thakker, D Gope, ...
Proceedings of Machine Learning and Systems 3, 517-532, 2021
762021
Managing cache memory in a parallel processing environment
D Wentzlaff, M Mattina, A Agarwal
US Patent 7,882,307, 2011
762011
Caching in multicore and multiprocessor architectures
A Agarwal, IR Bratt, M Mattina
US Patent 7,805,575, 2010
752010
Federated learning based on dynamic regularization
DAE Acar, Y Zhao, RM Navarro, M Mattina, PN Whatmough, V Saligrama
arXiv preprint arXiv:2111.04263, 2021
702021
Euphrates: Algorithm-soc co-design for low-power mobile continuous vision
Y Zhu, A Samajdar, M Mattina, P Whatmough
arXiv preprint arXiv:1803.11232, 2018
702018
Flow control method and apparatus for single packet arrival on a bidirectional ring interconnect
M Mattina
US Patent 7,551,564, 2009
602009
Managing memory access in a parallel processing environment
M Mattina, D Wentzlaff, A Agarwal
US Patent 7,805,577, 2010
572010
Apparatus and method for partitioning a shared cache of a chip multi-processor
M Mattina, A Juan-Hormigo, J Emer, R Matas-Navarro
US Patent 7,558,920, 2009
492009
Fixynn: Efficient hardware for mobile computer vision via transfer learning
PN Whatmough, C Zhou, P Hansen, SK Venkataramanaiah, J Seo, ...
arXiv preprint arXiv:1902.11128, 2019
442019
Multiprocessor chip having bidirectional ring interconnect
G Chrysos, M Mattina, S Felix
US Patent App. 10/855,509, 2006
442006
Managing set associative cache memory according to entry type
D Wentzlaff, M Mattina, A Agarwal
US Patent 7,461,210, 2008
412008
A systematic methodology for characterizing scalability of dnn accelerators using scale-sim
A Samajdar, JM Joseph, Y Zhu, P Whatmough, M Mattina, T Krishna
2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020
382020
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