| On-chip interconnection architecture of the tile processor D Wentzlaff, P Griffin, H Hoffmann, L Bao, B Edwards, C Ramey, ... IEEE micro 27 (5), 15-31, 2007 | 1097 | 2007 |
| Tile64-processor: A 64-core soc with mesh interconnect S Bell, B Edwards, J Amann, R Conlin, K Joyce, V Leung, J MacKay, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 812 | 2008 |
| Computing in parallel processing environments PR Griffin, M Hostetter, A Agarwal, CC Miao, CD Metcalf, B Edwards, ... US Patent 8,738,860, 2014 | 244 | 2014 |
| Last level cache (llc) performance of data mining workloads on a cmp-a case study of parallel bioinformatics workloads A Jaleel, M Mattina, B Jacob The Twelfth International Symposium on High-Performance Computer …, 2006 | 174 | 2006 |
| Scale-sim: Systolic cnn accelerator simulator A Samajdar, Y Zhu, P Whatmough, M Mattina, T Krishna arXiv preprint arXiv:1811.02883, 2018 | 144 | 2018 |
| Tarantula: A vector extension to the alpha architecture R Espasa, F Ardanaz, J Emer, S Felix, J Gago, R Gramunt, I Hernandez, ... Proceedings 29th Annual International Symposium on Computer Architecture …, 2002 | 135 | 2002 |
| Caching in multicore and multiprocessor architectures A Agarwal, IR Bratt, M Mattina US Patent 7,805,575, 2010 | 80 | 2010 |
| Managing cache memory in a parallel processing environment D Wentzlaff, M Mattina, A Agarwal US Patent 7,882,307, 2011 | 75 | 2011 |
| Caching in multicore and multiprocessor architectures A Agarwal, IR Bratt, M Mattina US Patent 7,805,575, 2010 | 75 | 2010 |
| Flow control method and apparatus for single packet arrival on a bidirectional ring interconnect M Mattina US Patent 7,551,564, 2009 | 60 | 2009 |
| Euphrates: Algorithm-soc co-design for low-power mobile continuous vision Y Zhu, A Samajdar, M Mattina, P Whatmough arXiv preprint arXiv:1803.11232, 2018 | 58 | 2018 |
| Managing memory access in a parallel processing environment M Mattina, D Wentzlaff, A Agarwal US Patent 7,805,577, 2010 | 57 | 2010 |
| Sparse: Sparse architecture search for cnns on resource-constrained microcontrollers I Fedorov, RP Adams, M Mattina, PN Whatmough arXiv preprint arXiv:1905.12107, 2019 | 54 | 2019 |
| Apparatus and method for partitioning a shared cache of a chip multi-processor M Mattina, A Juan-Hormigo, J Emer, R Matas-Navarro US Patent 7,558,920, 2009 | 49 | 2009 |
| Multiprocessor chip having bidirectional ring interconnect G Chrysos, M Mattina, S Felix US Patent App. 10/855,509, 2006 | 44 | 2006 |
| Managing set associative cache memory according to entry type D Wentzlaff, M Mattina, A Agarwal US Patent 7,461,210, 2008 | 41 | 2008 |
| Protocol for maintaining cache coherency in a CMP M Mattina, GZ Chrysos US Patent 8,209,490, 2012 | 37 | 2012 |
| Caching in multicore and multiprocessor architectures A Agarwal, IR Bratt, M Mattina US Patent 7,853,755, 2010 | 37 | 2010 |
| Fixynn: Efficient hardware for mobile computer vision via transfer learning PN Whatmough, C Zhou, P Hansen, SK Venkataramanaiah, J Seo, ... arXiv preprint arXiv:1902.11128, 2019 | 35 | 2019 |
| Condensed router headers with low latency output port calculation IR Bratt, CG Ramey, M Mattina US Patent 8,572,353, 2013 | 33 | 2013 |
Paul N WhatmoughArm ML Research Lab, Harvard UniversityVerified email at arm.com
