Arindam Mallik
Arindam Mallik
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The Complementary FET (CFET) for CMOS scaling beyond N3
J Ryckaert, P Schuddinck, P Weckx, G Bouche, B Vincent, J Smith, ...
2018 IEEE Symposium on Vlsi Technology, 141-142, 2018
System and method for controlling power consumption in a computer system based on user satisfaction
L Yang, RP Dick, X Chen, G Memik, PA Dinda, A Shye, B Ozisikyilmaz, ...
US Patent 8,706,652, 2014
Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming
D Cordes, P Marwedel, A Mallik
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardwareá…, 2010
PICSEL: Measuring user-perceived performance to control dynamic frequency scaling
A Mallik, J Cosgrove, RP Dick, G Memik, P Dinda
Proceedings of the 13th international conference on Architectural supportá…, 2008
Towards 10000TOPS/W DNN inference with analog in-memory computing–a circuit blueprint, device options and requirements
S Cosemans, B Verhoef, J Doevenspeck, IA Papistas, F Catthoor, ...
2019 IEEE International Electron Devices Meeting (IEDM), 22.2. 1-22.2. 4, 2019
User-driven frequency scaling
A Mallik, B Lin, G Memik, P Dinda, RP Dick
IEEE Computer Architecture Letters 5 (2), 16-16, 2006
SOT-MRAM based analog in-memory computing for DNN inference
J Doevenspeck, K Garello, B Verhoef, R Degraeve, S Van Beek, D Crotti, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
Learning and leveraging the relationship between architecture-level measurements and individual user satisfaction
A Shye, B Ozisikyilmaz, A Mallik, G Memik, PA Dinda, RP Dick, ...
ACM SIGARCH Computer Architecture News 36 (3), 427-438, 2008
Engineering over-clocking: Reliability-performance trade-offs for high-performance register files
G Memik, MH Chowdhury, A Mallik, YI Ismail
2005 International Conference on Dependable Systems and Networks (DSN'05á…, 2005
DTCO including sustainability: Power-performance-area-cost-environmental score (PPACE) analysis for logic technologies
MG Bardon, P Wuytens, L┼ Ragnarsson, G Mirabelli, D Jang, G Willems, ...
2020 IEEE International Electron Devices Meeting (IEDM), 41.4. 1-41.4. 4, 2020
The impact of sequential-3D integration on semiconductor scaling roadmap
A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017
User-and process-driven dynamic voltage and frequency scaling
B Lin, A Mallik, P Dinda, G Memik, R Dick
2009 IEEE International Symposium on Performance Analysis of Systems andá…, 2009
DIANA: An end-to-end energy-efficient digital and ANAlog hybrid neural network SoC
K Ueyoshi, IA Papistas, P Houshmand, GM Sarda, V Jain, M Shi, Q Zheng, ...
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022
Low-power optimization by smart bit-width allocation in a SystemC-based ASIC design environment
A Mallik, D Sinha, P Banerjee, H Zhou
IEEE Transactions on Computer-Aided Design of Integrated Circuits andá…, 2007
The user in experimental computer systems research
PA Dinda, G Memik, RP Dick, B Lin, A Mallik, A Gupta, S Rossoff
Proceedings of the 2007 workshop on experimental computer science, 10-es, 2007
Maintaining Moore’s law: enabling cost-friendly dimensional scaling
A Mallik, J Ryckaert, A Mercha, D Verkest, K Ronse, A Thean
Extreme Ultraviolet (EUV) Lithography VI 9422, 531-542, 2015
Systems and methods for process and user driven dynamic voltage and frequency scaling
A Mallik, B Lin, G Memik, P Dinda, R Dick
US Patent 7,913,071, 2011
Analog in-memory computing in FeFET-based 1T1R array for edge AI applications
D Saito, T Kobayashi, H Koga, N Ronchi, K Banerjee, Y Shuto, J Okuno, ...
2021 Symposium on VLSI Technology, 1-2, 2021
A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration
IA Papistas, S Cosemans, B Rooseleer, J Doevenspeck, MH Na, A Mallik, ...
2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021
Design-technology co-optimization for OxRRAM-based synaptic processing unit
A Mallik, D Garbin, A Fantini, D Rodopoulos, R Degraeve, J Stuijt, AK Das, ...
2017 Symposium on VLSI Technology, T178-T179, 2017
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