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M. Akif Özkan
M. Akif Özkan
Cadence Design Systems
Verified email at fau.de - Homepage
Title
Cited by
Cited by
Year
Generating FPGA-based image processing accelerators with Hipacc
O Reiche, MA Özkan, R Membarth, J Teich, F Hannig
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD …, 2017
442017
FPGA-based accelerator design from a domain-specific language
MA Özkan, O Reiche, F Hannig, J Teich
2016 26th International Conference on Field Programmable Logic and …, 2016
392016
Secure voice communication via GSM network
MA Ozkan, B Ors, G Saldamli
2011 7th International Conference on Electrical and Electronics Engineering …, 2011
252011
AnyHLS: High-level synthesis with partial evaluation
MA Özkan, A Pérard-Gayot, R Membarth, P Slusallek, R Leißa, S Hack, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
222020
Using high-level synthesis for rapid design of video processing pipes
AE Guzel, VE Levent, M Tosun, MA Özkan, T Akgun, D Büyükaydin, ...
2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016
142016
Data Transmission via GSM Voice Channel for End to End Security
MA Ozkan, SB Ors
IEEE International Conference on Consumer Electronics – Berlin, (ICCE-Berlin), 2015
132015
A highly efficient and comprehensive image processing library for C++-based high-level synthesis
MA Özkan, O Reiche, F Hannig, J Teich
FSP 2017; Fourth International Workshop on FPGAs for Software Programmers, 1-10, 2017
112017
Efficient hardware acceleration of sparsely active convolutional spiking neural networks
J Sommer, MA Özkan, O Keszocze, J Teich
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022
102022
Loop parallelization techniques for fpga accelerator synthesis
O Reiche, MA Özkan, F Hannig, J Teich, M Schmid
Journal of Signal Processing Systems 90, 3-27, 2018
102018
Hardware design and analysis of efficient loop coarsening and border handling for image processing
MA Özkan, O Reiche, F Hannig, J Teich
2017 IEEE 28th International Conference on Application-specific Systems …, 2017
92017
HipaccVX: wedding of OpenVX and DSL-based code generation
MA Özkan, B Ok, B Qiao, J Teich, F Hannig
Journal of Real-Time Image Processing 18, 765-777, 2021
82021
The best of both worlds: Combining CUDA graph with an image processing DSL
B Qiao, MA Özkan, J Teich, F Hannig
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
82020
Dsp-packing: Squeezing low-precision arithmetic into fpga dsp blocks
J Sommer, MA Özkan, O Keszocze, J Teich
2022 32nd International Conference on Field-Programmable Logic and …, 2022
62022
Rapid design of real-time image fusion on FPGA using HLS and other techniques
F Aydin, HF Ugurdag, VE Levent, AE Guzel, NFR Annafianto, MA Ozkan, ...
2018 IEEE/ACS 15th International Conference on Computer Systems and …, 2018
52018
Hybrid code description for developing fast and resource efficient image processing architectures
K Häublein, M Reichenbach, O Reiche, MA Özkan, D Fey, F Hannig, ...
2016 International Conference on Embedded Computer Systems: Architectures …, 2016
42016
Area-efficient look-up tables for semi-randomly accessible functions
H Unlu, MA Ozkan, HF Ugurdag, E Adali
Proc. of WSEAS Recent Advances in Electrical Engineering, 171-174, 2014
22014
Efficient parallel reduction on GPUs with Hipacc
B Qiao, O Reiche, MA Özkan, J Teich, F Hannig
Proceedings of the 23th International Workshop on Software and Compilers for …, 2020
12020
A journey into DSL design using generative programming: FPGA mapping of image border handling through refinement
MA Özkan, A Pérard-Gayot, R Membarth, P Slusallek, J Teich, F Hannig
FSP Workshop 2018; Fifth International Workshop on FPGAs for Software …, 2018
12018
Fast one-and two-pick fixed-priority selection and muxing circuits
M Tosun, MA Özkan, AE Güzel, HF Ugurdag
2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016
12016
Implementation Of A Lightweight Trusted Platform Module
MA Özkan
Fen Bilimleri Enstitüsü, 2014
12014
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Articles 1–20