| Test, validation, and debug architecture MB Trobough, KK Tiruvallur, CB Prudvi, CE Iovin, DW Grawrock, ... US Patent 10,198,333, 2019 | 41 | 2019 |
| Automatic self test of an integrated circuit component via AC I/O loopback B Querbach, DG Ellis, A Khan, MJ Tripp, ES Gayles, E Gollapudi US Patent 7,139,957, 2006 | 31 | 2006 |
| Push button mode automatic pattern switching for interconnect built-in self test DG Ellis, B Querbach, JJ Nejedlo, A Khan, SR Babcock, ES Gayles, ... US Patent 6,826,100, 2004 | 28 | 2004 |
| Integrated circuit defect detection and repair B Querbach, WK Lui, DG Ellis, DJ Zimmerman, TZ Schoenborn, ... US Patent 9,548,137, 2017 | 21 | 2017 |
| Architecture of a reusable BIST engine for detection and autocorrection of memory failures and for IO debug, validation, link training, and power optimization on 14-nm SoC B Querbach, R Khanna, S Puligundla, D Blankenbeckler, J Crop, ... IEEE Design & Test 33 (1), 59-67, 2015 | 18 | 2015 |
| Robust memory link testing using memory controller BL Spry, TZ Schoenborn, P Abraham, CP Mozak, DG Ellis, JJ Nejedlo, ... US Patent 8,868,992, 2014 | 18 | 2014 |
| Supporting multiple memory types in a memory slot W Han, M Arafa, BS Morris, M Prakash, JK Pickett, JK Grooms, ... US Patent 10,163,508, 2018 | 16 | 2018 |
| A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time B Querbach, R Khanna, D Blankenbeckler, Y Zhang, RT Anderson, ... 2014 International Test Conference, 1-10, 2014 | 14 | 2014 |
| Methods and apparatuses for validating AC I/O loopback tests using delay modeling in RTL simulation B Querbach, A Khan, M Tripp, LB Guerrero, MAV Vargas, A Muhtaroglu US Patent 7,228,515, 2007 | 11 | 2007 |
| Pre-announce signaling for interconnect built-in self test D Ellis, B Querbach, J Nejedlo, A Khan, S Babcock, E Gayles, E Gollapudi US Patent App. 10/404,949, 2004 | 11 | 2004 |
| Integrated circuit reliability assessment apparatus and method CF Connor, B Querbach, G McFadden, HP Belgal, R Khanna US Patent App. 14/961,824, 2017 | 10 | 2017 |
| Comparison of hardware based and software based stress testing of memory IO interface B Querbach, S Puligundla, D Becerra, ZT Schoenborn, P Chiang 2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013 | 8 | 2013 |
| Regulating a timing between a strobe signal and a data signal B Querbach, MA Abdallah, AMA Khan, MM Hossain, SM Sarkar US Patent 7,480,360, 2009 | 8 | 2009 |
| Integrated circuit reliability assessment apparatus and method CF Connor, B Querbach, G McFadden, R Khanna US Patent 9,977,075, 2018 | 6 | 2018 |
| Memory controller-controlled refresh abort B Querbach, KS Bains, JB Halbert US Patent 9,953,694, 2018 | 6 | 2018 |
| Extended platform with additional memory module slots per CPU socket B Querbach, PD Vogt US Patent 9,818,457, 2017 | 6 | 2017 |
| Rack scale architecture (rsa) and shared memory controller (smc) techniques of fast zeroing B Querbach, MA Schmisseur, RK Ramanujan, M Arafa, CF Connor, ... US Patent App. 14/752,826, 2016 | 6 | 2016 |
| Integrated circuit defect detection and repair B Querbach, TZ Schoenborn, DJ Zimmerman, DG Ellis, CW Hampson, ... US Patent 9,564,245, 2017 | 5 | 2017 |
| Voltage margining with a low power, high speed, input offset cancelling equalizer B Querbach, RB Hamilton, LA Johnson, M Kim US Patent 7,501,863, 2009 | 5 | 2009 |
| Selective performance level modes of operation in a non-volatile memory CF Connor, B Querbach, HP Belgal US Patent 10,163,502, 2018 | 4 | 2018 |
Rahul Khanna, PhDIntel Principal EngineerVerified email at ieee.org
