| Minimally biased multipliers for approximate integer and floating-point multiplication H Saadat, H Bokhari, S Parameswaran IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 81 | 2018 |
| darknoc: Designing energy-efficient network-on-chip with multi-vt cells for dark silicon H Bokhari, H Javaid, M Shafique, J Henkel, S Parameswaran Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 74 | 2014 |
| Layer-based operations scheduling to optimise memory for CNN applications JA Ambrose, I Ahmed, Y Yachide, H Bokhari, J Peddersen, ... US Patent 10,740,674, 2020 | 52 | 2020 |
| Supernet: multimode interconnect architecture for manycore chips H Bokhari, H Javaid, M Shafique, J Henkel, S Parameswaran Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 26 | 2015 |
| Malleable NoC: Dark silicon inspired adaptable network-on-chip H Bokhari, H Javaid, M Shafique, J Henkel, S Parameswaran 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 23 | 2015 |
| Memory access optimisation using per-layer computational mapping and memory allocation for CNN application H Bokhari, J Peddersen, S Parameswaran, I Ahmed, Y Yachide AU Patent App. 2,017,279,610, 0 | 23* | |
| Dark Silicon: From Computation to Communication J Henkel, H Bokhari, S Garg, MUK Khan, H Khdr, F Kriebel, ÜY Ogras, ... 9th International Symposium on Networks-on-Chip, NOCS'15, 2015 | 16 | 2015 |
| Network-on-Chip Design. H Bokhari, S Parameswaran, S Ha, J Teich Handbook of Hardware/Software Codesign, 461-489, 2017 | 7 | 2017 |
| FALCON: A framework for hierarchical computation of metrics for component-based parameterized SoCs H Javaid, Y Yachide, SMM Shwe, H Bokhari, S Parameswaran Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 4 | 2014 |
| Adroit use of dark silicon for power, performance and reliability optimisation of NoCs H Bokhari, M Shafique, J Henkel, S Parameswaran The Dark Side of Silicon: Energy Efficient Computing in the Dark Silicon Era …, 2017 | 1 | 2017 |
| Power, performance and reliability optimisation of on-chip interconnect by adroit use of dark silicon H Bokhari UNSW Sydney, 2015 | | 2015 |
| System-level optimization of on-chip communication using express links for throughput constrained MPSoCs H Bokhari, H Javaid, S Parameswaran The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 68-77, 2013 | | 2013 |
