| Innovative materials, devices, and CMOS technologies for low-power mobile multimedia T Skotnicki, C Fenouillet-Beranger, C Gallon, F Boeuf, S Monfray, F Payet, ... IEEE transactions on electron devices 55 (1), 96-130, 2007 | 270 | 2007 |
| A commercial 65nm CMOS technology for space applications: Heavy ion, proton and gamma test results and modeling P Roche, G Gasiot, S Uznanski, JM Daveau, J Torras-Flaquer, S Clerc, ... 2009 European Conference on Radiation and Its Effects on Components and …, 2009 | 69 | 2009 |
| A 460 mhz at 397 mv, 2.6 ghz at 1.3 v, 32 bits vliw dsp embedding f max tracking E Beigne, A Valentian, I Miro-Panades, R Wilson, P Flatresse, F Abouzeid, ... IEEE Journal of Solid-State Circuits 50 (1), 125-136, 2014 | 60 | 2014 |
| 8.4 a 0.33 v/-40 c process/temperature closed-loop compensation soc embedding all-digital clock multiplier and dc-dc converter exploiting fdsoi 28nm back-gate biasing S Clerc, M Saligane, F Abouzeid, M Cochet, JM Daveau, C Bottoni, D Bol, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 53 | 2015 |
| A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking R Wilson, E Beigne, P Flatresse, A Valentian, F Abouzeid, T Benoist, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 52 | 2014 |
| Scalable 0.35 V to 1.2 V SRAM bitcell design from 65 nm CMOS to 28 nm FDSOI F Abouzeid, A Bienfait, KC Akyel, A Feki, S Clerc, L Ciampolini, F Giner, ... IEEE Journal of Solid-State Circuits 49 (7), 1499-1505, 2014 | 43 | 2014 |
| Detailed SET measurement and characterization of a 65 nm bulk technology M Glorieux, A Evans, V Ferlet-Cavrois, C Boatella-Polo, D Alexandrescu, ... IEEE Transactions on Nuclear Science 64 (1), 81-88, 2016 | 40 | 2016 |
| Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs E Beigné, A Valentian, B Giraud, O Thomas, T Benoist, Y Thonnart, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 613-618, 2013 | 37 | 2013 |
| The Fourth Terminal: Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems S Clerc, A Cathelin, T Di-Giglio Springer Nature, 2020 | 36 | 2020 |
| A 225 μm Probe Single-Point Calibration Digital Temperature Sensor Using Body-Bias Adjustment in 28 nm FD-SOI CMOS M Cochet, B Keller, S Clerc, F Abouzeid, A Cathelin, JL Autran, P Roche, ... IEEE Solid-State Circuits Letters 1 (1), 14-17, 2018 | 35 | 2018 |
| New D-flip-flop design in 65 nm CMOS for improved SEU and low power overhead at system level M Glorieux, S Clerc, G Gasiot, JL Autran, P Roche IEEE Transactions on Nuclear Science 60 (6), 4381-4386, 2013 | 34 | 2013 |
| Heavy ions test result on a 65nm sparc-v8 radiation-hard microprocessor C Bottoni, M Glorieux, JM Daveau, G Gasiot, F Abouzeid, S Clerc, ... 2014 IEEE International Reliability Physics Symposium, 5F. 5.1-5F. 5.6, 2014 | 28 | 2014 |
| Random-walk drift-diffusion charge-collection model for reverse-biased junctions embedded in circuits M Glorieux, JL Autran, D Munteanu, S Clerc, G Gasiot, P Roche IEEE Transactions on Nuclear Science 61 (6), 3527-3534, 2014 | 24 | 2014 |
| 28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0 V, 10MHz/700MHz, 252bits frame error-decoder F Abouzeid, S Clerc, B Pelloux-Prayer, F Argoud, P Roche 2012 Proceedings of the ESSCIRC (ESSCIRC), 153-156, 2012 | 24 | 2012 |
| A 45nm CMOS 0.35 V-optimized standard cell library for ultra-low power applications F Abouzeid, S Clerc, F Firmin, M Renaudin, G Sicard Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009 | 23 | 2009 |
| Experimental characterization of process corners effect on SRAM alpha and neutron soft error rates G Gasiot, M Glorieux, S Uznanski, S Clerc, P Roche 2012 IEEE International Reliability Physics Symposium (IRPS), 3C. 4.1-3C. 4.5, 2012 | 19 | 2012 |
| Integrated circuit elementary cell with a low sensitivity to external disturbances S Clerc, G Gasiot, M Glorieux US Patent 8,497,701, 2013 | 18 | 2013 |
| A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation soft error tolerance S Clerc, F Abouzeid, G Gasiot, D Gauthier, P Roche 2012 Proceedings of the ESSCIRC (ESSCIRC), 313-316, 2012 | 18 | 2012 |
| Experimental soft error rate of several flip-flop designs representative of production chip in 32 nm CMOS technology G Gasiot, M Glorieux, S Clerc, D Soussan, F Abouzeid, P Roche IEEE Transactions on Nuclear Science 60 (6), 4226-4231, 2013 | 17 | 2013 |
| Space radiation and reliability qualifications on 65nm CMOS 600MHz microprocessors S Clerc, F Abouzeid, G Gasiot, JM Daveau, C Bottoni, M Glorieux, ... 2013 IEEE International Reliability Physics Symposium (IRPS), 6C. 1.1-6C. 1.7, 2013 | 16 | 2013 |
