Dimitrios Soudris
Dimitrios Soudris
Professor, Electrical & Computer Eng., National Technical Univ. of Athens
Verified email at microlab.ntua.gr - Homepage
Cited by
Cited by
A survey on FEC codes for 100 G and beyond optical networks
G Tzimpragos, C Kachris, IB Djordjevic, M Cvijetic, D Soudris, I Tomkos
IEEE Communications Surveys & Tutorials 18 (1), 209-221, 2014
Fine-and coarse-grain reconfigurable computing
S Vassiliadis, D Soudris
Springer, 2007
Designing CMOS circuits for low power
D Soudris, C Piguet, C Goutis
Springer Publishing Company, Incorporated, 2010
ECG signal analysis and arrhythmia detection on IoT wearable medical devices
D Azariadi, V Tsoutsouras, S Xydis, D Soudris
2016 5th International conference on modern circuits and systems …, 2016
Computation offloading and resource allocation for low-power IoT edge devices
F Samie, V Tsoutsouras, L Bauer, S Xydis, D Soudris, J Henkel
2016 IEEE 3rd World Forum on Internet of Things (WF-IoT), 7-12, 2016
A survey of coarse-grain reconfigurable architectures and cad tools
G Theodoridis, D Soudris, S Vassiliadis
Fine-and Coarse-Grain Reconfigurable Computing, 89-149, 2007
Three dimensional system integration: IC stacking process and design
A Papanikolaou, D Soudris, R Radojcic
Springer Science & Business Media, 2010
Design-efficient approximate multiplication circuits through partial product perforation
G Zervakis, K Tsoumanis, S Xydis, D Soudris, K Pekmestzi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10 …, 2016
Designing 2D and 3D network-on-chip architectures
K Tatas, K Siozios, D Soudris, A Jantsch
Springer, 2014
A survey on reconfigurable accelerators for cloud computing
C Kachris, D Soudris
2016 26th International conference on field programmable logic and …, 2016
A differential geometry approach for the workspace analysis of spherical parallel manipulators
G Yang
Proc. 11th World Cong. in Mechanism and Machine Science, Tianjin, 2004, 2060 …, 2004
The circuit design of multiple-valued logic voltage-mode adders
IM Thoidis, D Soudris, JM Fernandez, A Thanailakis
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001
Time and workload dependent device variability in circuit simulations
D Rodopoulos, SB Mahato, VV de Almeida Camargo, B Kaczer, ...
2011 IEEE International Conference on IC Design & Technology, 1-4, 2011
Systematic dynamic memory management design methodology for reduced memory footprint
D Atienza, JM Mendias, S Mamagkakis, D Soudris, F Catthoor
ACM Transactions on Design Automation of Electronic Systems (TODAES) 11 (2 …, 2006
Data-reuse and parallel embedded architectures for low-power, real-time multimedia applications
D Soudris, ND Zervas, A Argyriou, M Dasygenis, K Tatas, CE Goutis, ...
International Workshop on Power and Timing Modeling, Optimization and …, 2000
Architecture-level exploration of alternative interconnection schemes targeting 3d fpgas: A software-supported methodology
K Siozios, A Bartzas, D Soudris
International Journal of Reconfigurable Computing 2008, 2008
A heterogeneous multicore system on chip with run-time reconfigurable virtual FPGA architecture
M Hubner, P Figuli, R Girardey, D Soudris, K Siozios, J Becker
2011 IEEE International Symposium on Parallel and Distributed Processing …, 2011
High performance and area efficient flexible DSP datapath synthesis
S Xydis, G Economakos, D Soudris, K Pekmestzi
IEEE transactions on very large scale integration (VLSI) systems 19 (3), 429-442, 2009
Distributed run-time resource management for malleable applications on many-core platforms
I Anagnostopoulos, V Tsoutsouras, A Bartzas, D Soudris
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck
M Dasygenis, E Brockmeyer, B Durinck, F Catthoor, D Soudris, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (3), 279-291, 2006
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