Ramon Matas
Ramon Matas
Principal ML researcher @ ARM
Verified email at arm.com
Title
Cited by
Cited by
Year
Apparatus and method for partitioning a shared cache of a chip multi-processor
M Mattina, A Juan-Hormigo, J Emer, R Matas-Navarro
US Patent 7,558,920, 2009
492009
Boot strap processor assignment for a multi-core processing unit
SS Chang, A Thakur, R Sundararaman, R Matas, JS Lawlor, RF Netting
US Patent 9,658,861, 2017
222017
Simulating a chip multiprocessor with a symmetric multiprocessor
KC Barr, R Matas-Navarro, C Weaver, T Juan, J Emer
Boston Area Architecture Workshop, 2005
172005
Performing memory accesses using memory context information
R Matas
US Patent 8,521,944, 2013
102013
Micronets: Neural network architectures for deploying tinyml applications on commodity microcontrollers
C Banbury, C Zhou, I Fedorov, R Matas, U Thakker, D Gope, ...
Proceedings of Machine Learning and Systems 3, 2021
82021
Stateless capture of data linear addresses during precise event based sampling
R Gramunt, R Matas, BC Chaffin, NS Moyer, R Padmanabhan, AP Suprun, ...
US Patent 9,652,237, 2017
62017
Reset of multi-core processing system
SS Chang, A Thakur, R Sundararaman, R Matas
US Patent 9,389,657, 2016
62016
Reset of processing core in multi-core processing system
SS Chang, A Thakur, R Sundararaman, R Matas
US Patent 9,208,124, 2015
52015
Laminated siding panels having preselected colors
J Regelski, T Levendusky, G White
US Patent App. 10/318,427, 2004
32004
Advanced programmable interrupt controller identifier (APIC ID) assignment for a multi-core processing unit
SS Chang, A Thakur, R Sundararaman, R Matas, JS Lawlor, RF Netting
US Patent 9,372,816, 2016
22016
Federated learning based on dynamic regularization
DAE Acar, Y Zhao, RM Navarro, M Mattina, PN Whatmough, V Saligrama
International Conference on Learning Representations, 2021
12021
Scalable event handling in multi-threaded processor cores
R Gramunt, R Padmanabhan, R Matas, NS Moyer, BC Chaffin, A Sodani, ...
US Patent 9,886,396, 2018
12018
Memory fault suppression via re-execution and hardware FSM
R Matas, R Gramunt, C Chan, BC Chaffin, A Kesiraju, JC Hall, J Corbal
US Patent 9,715,432, 2017
12017
Initialization of multi-core processing system
SS Chang, A Thakur, RC Sundararaman, R Matas
US Patent 9,367,329, 2016
12016
Method and apparatus to share modified data without write-back in a shared-memory many-core system
R Sundararaman, JC Mejia, OM Rosell, J Antonio, R Matas
US Patent App. 13/731,584, 2014
12014
Collapsible Linear Blocks for Super-Efficient Super Resolution
K Bhardwaj, M Milosavljevic, A Chalfin, N Suda, L O'Neil, D Gope, L Meng, ...
arXiv preprint arXiv:2103.09404, 2021
2021
Dynamic partitioning of execution resources
JF Duluk Jr, L Durant, RM Navarro, A Menezes, J Tuckey, G Hirota, ...
US Patent 10,817,338, 2020
2020
Dynamic partitioning of execution resources
JF Duluk Jr, L Durant, RM Navarro, A Menezes, J Tuckey, G Hirota, ...
US Patent App. 15/885,751, 2019
2019
Resolving memory accesses crossing cache line boundaries
R Matas, C Chan, AP Suprun, A Kesiraju
US Patent 10,318,427, 2019
2019
Stateless capture of data linear addresses during precise event based sampling
R Gramunt, R Matas, BC Chaffin, NS Moyer, R Padmanabhan, AP Suprun, ...
US Patent 10,175,986, 2019
2019
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