koji inoue
koji inoue
Verified email at ait.kyushu-u.ac.jp - Homepage
Cited by
Cited by
Way-predicting set-associative cache for high performance and low energy consumption
K Inoue, T Ishihara, K Murakami
Proceedings of the 1999 international symposium on Low power electronics and …, 1999
Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing
Y Inadomi, T Patki, K Inoue, M Aoyagi, B Rountree, M Schulz, ...
SC'15: Proceedings of the International Conference for High Performance …, 2015
Multiplier energy reduction through bypassing of partial products
J Ohban, VG Moshnyaga, K Inoue
Asia-Pacific conference on circuits and systems 2, 13-17, 2002
Power and performance analysis of GPU-accelerated systems
Y Abe, H Sasaki, M Peres, K Inoue, K Murakami, S Kato
2012 Workshop on Power-Aware Computing and Systems (HotPower 12), 2012
Performance prediction of large-scale parallell system and application using macro-level simulation
R Susukita, H Ando, M Aoyagi, H Honda, Y Inadomi, K Inoue, S Ishizuki, ...
SC'08: Proceedings of the 2008 ACM/IEEE Conference on Supercomputing, 1-9, 2008
Power and performance characterization and modeling of GPU-accelerated systems
Y Abe, H Sasaki, S Kato, K Inoue, M Edahiro, M Peres
2014 IEEE 28th international parallel and distributed processing symposium …, 2014
Proposal of a desk-side supercomputer with reconfigurable data-paths using rapid single-flux-quantum circuits
N Takagi, K Murakami, A Fujimaki, N Yoshikawa, K Inoue, H Honda
IEICE transactions on electronics 91 (3), 350-355, 2008
Novel frontier of photonics for data processing—Photonic accelerator
K Kitayama, M Notomi, M Naruse, K Inoue, S Kawakami, A Uchida
APL Photonics 4 (9), 090901, 2019
Scalability-based manycore partitioning
H Sasaki, T Tanimoto, K Inoue, H Nakamura
Proceedings of the 21st international conference on Parallel architectures …, 2012
Dynamically variable line-size cache exploiting high on-chip memory bandwidth of merged DRAM/logic LSIs
K Inoue, K Kai, K Murakami
Proceedings Fifth International Symposium on High-Performance Computer …, 1999
Coordinated power-performance optimization in manycores
H Sasaki, S Imamura, K Inoue
Proceedings of the 22nd international conference on Parallel architectures …, 2013
A history-based I-cache for low-energy multimedia applications
K Inoue, VG Moshnyaga, K Murakarni
Proceedings of the International Symposium on Low Power Electronics and …, 2002
An architecture framework for an adaptive extensible processor
H Noori, F Mehdipour, K Murakami, K Inoue, MS Zamani
The Journal of Supercomputing 45 (3), 313-340, 2008
Production hardware overprovisioning: Real-world performance optimization using an extensible power-aware resource management framework
R Sakamoto, T Cao, M Kondo, K Inoue, M Ueda, T Patki, D Ellsworth, ...
2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2017
A high-performance and low-power cache architecture with speculative way-selection
K Inoue, T Ishihara, K Murakami
IEICE Transactions on Electronics 83 (2), 186-194, 2000
An operand routing network for an SFQ reconfigurable data-paths processor
I Kataeva, H Akaike, A Fujimaki, N Yoshikawa, N Takagi, K Inoue, ...
IEEE transactions on applied superconductivity 19 (3), 665-669, 2009
High bandwidth, variable line-size cache architecture for merged DRAM/logic LSIs
K Inoue, K Kai, K Murakami
IEICE Transactions on Electronics 81 (9), 1438-1447, 1998
Energy-security tradeoff in a secure cache architecture against buffer overflow attacks
K Inoue
ACM SIGARCH Computer Architecture News 33 (1), 81-89, 2005
Cache memory system with variable block-size mechanism
K Kai, K Inoue, K Murakami
US Patent 6,349,364, 2002
Low power cache design
VG Moshnyaga, K Inoue
Low-Power Electronics Design, 2006
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