| Design-efficient approximate multiplication circuits through partial product perforation G Zervakis, K Tsoumanis, S Xydis, D Soudris, K Pekmestzi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10 …, 2016 | 75 | 2016 |
| Approximate hybrid high radix encoding for energy-efficient inexact multipliers V Leon, G Zervakis, D Soudris, K Pekmestzi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 421-430, 2017 | 40 | 2017 |
| Delta DICE: A double node upset resilient latch N Eftaxiopoulos, N Axelos, G Zervakis, K Tsoumanis, K Pekmestzi 2015 IEEE 58th International Midwest Symposium on Circuits and Systems …, 2015 | 34 | 2015 |
| Walking through the energy-error Pareto frontier of approximate multipliers V Leon, G Zervakis, S Xydis, D Soudris, K Pekmestzi IEEE Micro 38 (4), 40-49, 2018 | 22 | 2018 |
| Hybrid approximate multiplier architectures for improved power-accuracy trade-offs G Zervakis, S Xydis, K Tsoumanis, D Soudris, K Pekmestzi 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 17 | 2015 |
| Approximate multiplier architectures through partial product perforation: Power-area tradeoffs analysis G Zervakis, K Tsoumanis, S Xydis, N Axelos, K Pekmestzi Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 229-232, 2015 | 15 | 2015 |
| Pre-encoded multipliers based on non-redundant radix-4 signed-digit encoding K Tsoumanis, N Axelos, N Moschopoulos, G Zervakis, K Pekmestzi IEEE Transactions on Computers 65 (2), 670-676, 2015 | 15 | 2015 |
| Multi-level approximate accelerator synthesis under voltage island constraints G Zervakis, S Xydis, D Soudris, K Pekmestzi IEEE Transactions on Circuits and Systems II: Express Briefs 66 (4), 607-611, 2018 | 10 | 2018 |
| Flexible DSP accelerator architecture exploiting carry-save arithmetic K Tsoumanis, S Xydis, G Zervakis, K Pekmestzi IEEE Transactions On Very Large Scale Integration (Vlsi) Systems 24 (1), 368-372, 2015 | 10 | 2015 |
| VADER: Voltage-driven netlist pruning for cross-layer approximate arithmetic circuits G Zervakis, K Koliogeorgi, D Anagnostos, N Zompakis, K Siozios IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (6 …, 2019 | 9 | 2019 |
| Vossim: A framework for enabling fast voltage overscaling simulation for approximate computing circuits G Zervakis, F Ntouskas, S Xydis, D Soudris, K Pekmestzi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (6 …, 2018 | 5 | 2018 |
| AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics K Koliogeorgi, D Masouros, G Zervakis, S Xydis, T Becker, G Gaydadjiev, ... 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 362-367, 2017 | 5 | 2017 |
| A high radix Montgomery multiplier with concurrent error detection G Zervakis, N Eftaxiopoulos, K Tsoumanis, N Axelos, K Pekmestzi 2014 9th International Design and Test Symposium (IDT), 199-204, 2014 | 4 | 2014 |
| Performance-power exploration of software-defined big data analytics: The aegle cloud backend G Zervakis, S Xydis, D Soudris 2016 International Conference on Embedded Computer Systems: Architectures …, 2016 | 3 | 2016 |
| A radiation tolerant and self-repair memory cell N Eftaxiopoulos-Sarris, G Zervakis, K Tsoumanis, K Pekrnestzi 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 210-215, 2013 | 3 | 2013 |
| Weight-oriented approximation for energy-efficient neural network inference accelerators ZG Tasoulas, G Zervakis, I Anagnostopoulos, H Amrouch, J Henkel IEEE Transactions on Circuits and Systems I: Regular Papers 67 (12), 4670-4683, 2020 | 2 | 2020 |
| Design automation of approximate circuits with runtime reconfigurable accuracy G Zervakis, H Amrouch, J Henkel IEEE access 8, 53522-53538, 2020 | 2 | 2020 |
| Multi-level approximation for Inexact accelerator synthesis under voltage island constraints G Zervakis, S Xydis, V Tsoutsouras, D Soudris, K Pekmestzi Proc. Workshop Approx. Comput., 2016 | 2 | 2016 |
| On Accelerating Data Analytics: An Introduction to the Approximate Computing Technique G Zervakis IoT for Smart Grids, 163-180, 2019 | 1 | 2019 |
| An independent dual gate SOI FinFET soft-error resilient memory cell N Eftaxiopoulos, N Axelos, G Zervakis, K Tsoumanis, K Pekmestzi 2014 9th International Design and Test Symposium (IDT), 39-44, 2014 | 1 | 2014 |
Kiamal PekmestziEmeritus Professor, Electrical & Computer Eng., National Technical Univ. of AthensVerified email at cs.ntua.gr
