Follow
Dimitrios Garyfallou
Dimitrios Garyfallou
Postdoctoral Researcher, ECE Department, University of Thessaly, Greece
Verified email at e-ce.uth.gr - Homepage
Title
Cited by
Cited by
Year
Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance
D Garyfallou, S Simoglou, N Sketopoulos, C Antoniadis, CP Sotiriou, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (5), 962-972, 2021
92021
Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation
D Garyfallou, I Tsiokanos, N Evmorfopoulos, G Stamoulis, ...
2020 21st International Symposium on Quality Electronic Design (ISQED), 225-230, 2020
92020
Heuristics to augment the performance of Tetris legalization: making a fast but inferior method competitive
AN Dadaliaris, P Oikonomou, MG Koziri, E Nerantzaki, Y Hatzaras, ...
Journal of Low Power Electronics 13 (2), 220-230, 2017
92017
A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit Simulation on GPU s
D Garyfallou, N Evmorfopoulos, G Stamoulis
2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018
72018
A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects
D Garyfallou, C Antoniadis, N Evmorfopoulos, G Stamoulis
2019 16th International Conference on Synthesis, Modeling, Analysis and …, 2019
52019
EVT-based worst case delay estimation under process variation
C Antoniadis, D Garyfallou, N Evmorfopoulos, G Stamoulis
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
52018
Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models
C Chatzigeorgiou, D Garyfallou, G Floros, N Evmorfopoulos, G Stamoulis
2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 773-778, 2021
42021
Large scale circuit simulation exploiting combinatorial multigrid on massively parallel architectures
D Garyfallou, N Evmorfopoulos, G Stamoulis
2018 7th International Conference on Modern Circuits and Systems …, 2018
22018
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
D Garyfallou, A Vagenas, C Antoniadis, Y Massoud, G Stamoulis
Proceedings of the Great Lakes Symposium on VLSI 2022, 77-83, 2022
2022
The Extended and Asymmetric Extended Krylov Subspace in Moment-Matching-Based Order Reduction of Large Circuit Models
P Stoikos, D Garyfallou, G Floros, N Evmorfopoulos, G Stamoulis
arXiv preprint arXiv:2204.02467, 2022
2022
Novel techniques for timing analysis of VLSI circuits in advanced technology nodes
D Garyfallou
University of Thessaly, 2022
2022
Frequency-Limited Reduction of RLCK Circuits via Second-Order Balanced Truncation
O Axelou, D Garyfallou, G Floros
SMACD/PRIME 2021; International Conference on SMACD and 16th Conference on …, 2021
2021
Υλοποίηση και βελτιστοποίηση συνδυαστικού γραφοθεωρητικού αλγορίθμου για προσομοίωση πολύς μεγάλης κλίμακας γραμμικών κυκλωμάτων σε μαζικά παράλληλες αρχιτεκτονικές
ΔΚ Γαρυφάλλου
2015
Προσομοίωση κυκλωμάτων μεγάλης κλίμακας με προρυθμιστές Steiner κόμβων σε παράλληλες αρχιτεκτονικές
ΔΚ Γαρυφάλλου
2015
The system can't perform the operation now. Try again later.
Articles 1–14