| Mr. Wolf: An energy-precision scalable parallel ultra low power SoC for IoT edge processing A Pullini, D Rossi, I Loi, G Tagliavini, L Benini IEEE Journal of Solid-State Circuits 54 (7), 1970-1981, 2019 | 162 | 2019 |
| PULP: A parallel ultra low power platform for next generation IoT applications D Rossi, F Conti, A Marongiu, A Pullini, I Loi, M Gautschi, G Tagliavini, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-39, 2015 | 152 | 2015 |
| A transprecision floating-point platform for ultra-low power computing G Tagliavini, S Mach, D Rossi, A Marongiu, L Benini 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 131 | 2018 |
| Dory: Automatic end-to-end deployment of real-world dnns on low-cost iot mcus A Burrello, A Garofalo, N Bruschi, G Tagliavini, D Rossi, F Conti IEEE Transactions on Computers 70 (8), 1253-1268, 2021 | 124 | 2021 |
| The transprecision computing paradigm: Concept, design, and applications ACI Malossi, M Schaffner, A Molnos, L Gammaitoni, G Tagliavini, ... 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 91 | 2018 |
| Vega: A ten-core SoC for IoT endnodes with DNN acceleration and cognitive wake-up from MRAM-based state-retentive sleep mode D Rossi, F Conti, M Eggiman, A Di Mauro, G Tagliavini, S Mach, ... IEEE Journal of Solid-State Circuits 57 (1), 127-139, 2021 | 82 | 2021 |
| XpulpNN: Accelerating quantized neural networks on RISC-V processors through ISA extensions A Garofalo, G Tagliavini, F Conti, D Rossi, L Benini 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 186-191, 2020 | 57 | 2020 |
| Biowolf: A sub-10-mw 8-channel advanced brain–computer interface platform with a nine-core processor and ble connectivity V Kartsch, G Tagliavini, M Guermandi, S Benatti, D Rossi, L Benini IEEE transactions on biomedical circuits and systems 13 (5), 893-906, 2019 | 51 | 2019 |
| 4.4 A 1.3 TOPS/W@ 32GOPS fully integrated 10-core SoC for IoT end-nodes with 1.7 μW cognitive wake-up from MRAM-based state-retentive sleep mode D Rossi, F Conti, M Eggiman, S Mach, A Di Mauro, M Guermandi, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 60-62, 2021 | 48 | 2021 |
| A transprecision floating-point architecture for energy-efficient embedded computing S Mach, D Rossi, G Tagliavini, A Marongiu, L Benini 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 48 | 2018 |
| GVSoC: a highly configurable, fast and accurate full-platform simulator for RISC-V based IoT processors N Bruschi, G Haugou, G Tagliavini, F Conti, L Benini, D Rossi 2021 IEEE 39th International Conference on Computer Design (ICCD), 409-416, 2021 | 44 | 2021 |
| Flexfloat: A software library for transprecision computing G Tagliavini, A Marongiu, L Benini IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 41 | 2018 |
| Exploring architectural heterogeneity in intelligent vision systems N Chandramoorthy, G Tagliavini, K Irick, A Pullini, S Advani, S Al Habsi, ... 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 39 | 2015 |
| Xpulpnn: Enabling energy efficient and flexible inference of quantized neural networks on risc-v based iot end nodes A Garofalo, G Tagliavini, F Conti, L Benini, D Rossi IEEE Transactions on Emerging Topics in Computing 9 (3), 1489-1505, 2021 | 38 | 2021 |
| A mixed-precision RISC-V processor for extreme-edge DNN inference G Ottavi, A Garofalo, G Tagliavini, F Conti, L Benini, D Rossi 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 512-517, 2020 | 38 | 2020 |
| Design and evaluation of SmallFloat SIMD extensions to the RISC-V ISA G Tagliavini, S Mach, D Rossi, A Marongiu, L Benini 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 654-657, 2019 | 36 | 2019 |
| Unleashing fine-grained parallelism on embedded many-core accelerators with lightweight OpenMP tasking G Tagliavini, D Cesarini, A Marongiu IEEE Transactions on Parallel and Distributed Systems 29 (9), 2150-2163, 2018 | 33 | 2018 |
| Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters P Burgio, G Tagliavini, A Marongiu, L Benini 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 31 | 2013 |
| ADRENALINE: an OpenVX environment to optimize embedded vision applications on many-core accelerators G Tagliavini, G Haugou, A Marongiu, L Benini 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core …, 2015 | 30 | 2015 |
| Simplifying many-core-based heterogeneous SoC programming with offload directives A Marongiu, A Capotondi, G Tagliavini, L Benini IEEE Transactions on Industrial Informatics 11 (4), 957-967, 2015 | 29 | 2015 |
Luca BeniniETH Zürich, Università di BolognaVerified email at unibo.it
