Παρακολούθηση
UGUEN Yohann
UGUEN Yohann
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα intel.com - Αρχική σελίδα
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Παρατίθεται από
Παρατίθεται από
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Posits: the good, the bad and the ugly
F De Dinechin, L Forget, JM Muller, Y Uguen
Proceedings of the Conference for Next Generation Arithmetic 2019, 1-10, 2019
1022019
Evaluating the hardware cost of the posit number system
Y Uguen, L Forget, F de Dinechin
2019 29th International Conference on Field Programmable Logic and …, 2019
632019
Design-space exploration for the Kulisch accumulator
Y Uguen, F de Dinechin
172017
Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations
Y Uguen, F de Dinechin, S Derrien
2017 27th International Conference on Field Programmable Logic and …, 2017
152017
PyGA: a Python to FPGA compiler prototype
Y Uguen, E Petit
Proceedings of the 5th ACM SIGPLAN international workshop on artificial …, 2018
112018
Application-specific arithmetic in high-level synthesis tools
Y Uguen, FD Dinechin, V Lezaud, S Derrien
ACM Transactions on Architecture and Code Optimization (TACO) 17 (1), 1-23, 2020
102020
Hardware cost evaluation of the posit number system
L Forget, F de Dinechin
Compas' 2019-Conférence d'informatique en Parallélisme, Architecture et …, 2019
82019
A type-safe arbitrary precision arithmetic portability layer for HLS tools
L Forget, Y Uguen, F de Dinechin, D Thomas
Proceedings of the 10th International Symposium on Highly-Efficient …, 2019
72019
Comparing posit and IEEE-754 hardware cost
L Forget, Y Uguen, F de Dinechin
62021
High-level synthesis and arithmetic optimizations
Y Uguen
Université de Lyon, 2019
22019
A high-level synthesis approach optimizing accumulations in floating-point programs using custom formats and operators
Y Uguen, F de Dinechin, S Derrien
2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017
22017
Exploration architecturale de l’accumulateur de kulisch
Y Uguen, F de Dinechin
Compas' 2017-Conférence d’informatique en Parallélisme, Architecture et …, 2017
12017
High-Level Synthesis Using Application-Specific Arithmetic: A Case Study
Y Uguen, F de Dinechin, S Derrien
12017
SPU-sim : A cycle accurate simulator for the Stencil Processing Unit
Y Uguen, S Rajopadhye
http://perso.eleves.ens-rennes.fr/~yugue555/SPU-sim.pdf, 2015
12015
High-level synthesis and arithmetic optimization applied to reductions
Y Uguen, F de Dinechin, S Derrien
http://perso.eleves.ens-rennes.fr/~yugue555/ArithHLS.pdf, 2016
2016
Evaluating the hardware cost of posit arithmetic
L Forget, Y Uguen, F de Dinechin
HAL Id: hal-01488916
Y Uguen, F De Dinechin
Master research Internship
Y Uguen, F de Dinechin, S Derrien
Mise en oeuvre sur FPGA d’un processeur VLIW à l’aide d’outils de Synthèse de Haut-Niveau (Cairn Vex)
Y Uguen
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