| A survey on simulation-based fault injection tools for complex systems M Kooli, G Di Natale 2014 9th IEEE International Conference on Design & Technology of Integrated …, 2014 | 86 | 2014 |
| Cross-layer system reliability assessment framework for hardware faults A Vallero, A Savino, G Politano, S Di Carlo, A Chatzidimitriou, S Tselonis, ... 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 23 | 2016 |
| Computing reliability: On the differences between software testing and software fault injection techniques M Kooli, F Kaddachi, G Di Natale, A Bosio, P Benoit, L Torres Microprocessors and Microsystems 50, 102-112, 2017 | 12 | 2017 |
| Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview A Vallero, S Tselonis, N Foutris, M Kaliorakis, M Kooli, A Savino, ... Microprocessors and Microsystems 39 (8), 1204-1214, 2015 | 12 | 2015 |
| SyRA: Early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems A Vallero, A Savino, A Chatzidimitriou, M Kaliorakis, M Kooli, M Riera, ... IEEE Transactions on Computers 68 (5), 765-783, 2018 | 11 | 2018 |
| Cache-aware reliability evaluation through LLVM-based analysis and fault injection M Kooli, G Di Natale, A Bosio 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System …, 2016 | 11 | 2016 |
| Fault injection tools based on virtual machines M Kooli, P Benoit, G Di Natale, L Torres, V Sieh 2014 9th international symposium on reconfigurable and communication-centric …, 2014 | 11 | 2014 |
| Cache-and register-aware system reliability evaluation based on data lifetime analysis M Kooli, F Kaddachi, G Di Natale, A Bosio 2016 IEEE 34th VLSI Test Symposium (VTS), 1-6, 2016 | 9 | 2016 |
| Software testing and software fault injection M Kooli, A Bosio, P Benoit, L Torres 2015 10th International Conference on Design & Technology of Integrated …, 2015 | 9 | 2015 |
| Memory circuit capable of implementing calculation operations H Charles, M Kooli, JP Noel US Patent App. 16/684,987, 2020 | 8 | 2020 |
| System-level reliability evaluation through cache-aware software-based fault injection F Kaddachi, M Kooli, G Di Natale, A Bosio, M Ebrahimi, M Tahoori 2016 IEEE 19th International Symposium on Design and Diagnostics of …, 2016 | 6 | 2016 |
| Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces M Kooli, HP Charles, C Touzet, B Giraud, JP Noel 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 5 | 2018 |
| Software platform dedicated for in-memory computing circuit evaluation M Kooli, HP Charles, C Touzet, B Giraud, JP Noël 2017 International Symposium on Rapid System Prototyping (RSP), 43-49, 2017 | 5 | 2017 |
| Memory sizing of a scalable SRAM in-memory computing tile based architecture R Gauchi, M Kooli, P Vivet, JP Noel, E Beigné, S Mitra, HP Charles 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 4 | 2019 |
| Memory-aware design space exploration for reliability evaluation in computing systems M Kooli, G Di Natale, A Bosio Journal of Electronic Testing 35 (2), 145-162, 2019 | 4 | 2019 |
| Analysing and supporting the reliability decision-making process in computing systems with a reliability evaluation framework M Kooli Université Montpellier II, 2016 | 2 | 2016 |
| SCHIFI: Scalable and flexible high performance FPGA-based fault injector S Sau, M Kooli, G Di Natale, A Bosio, A Chakrabarti 2016 Conference on Design of Circuits and Integrated Systems (DCIS), 1-4, 2016 | 2 | 2016 |
| Early component-based system reliability analysis for approximate computing systems A Vallero, A Savino, G Politano, S Di Carlo, A Chatzidimitriou, S Tselonis, ... Proceedings Of The 2nd Workshop On Approximate Computing (WAPCO), 1-4, 2016 | 2 | 2016 |
| A 35.6 TOPS/W/mm˛ 3-stage pipelined computational SRAM with adjustable form factor for highly data-centric applications JP Noel, M Pezzin, R Gauchi, JF Christmann, M Kooli, HP Charles, ... IEEE Solid-State Circuits Letters 3, 286-289, 2020 | 1 | 2020 |
| Computational SRAM design automation using pushed-rule bitcells for energy-efficient vector processing JP Noel, V Egloff, M Kooli, R Gauchi, JM Portal, HP Charles, P Vivet, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 1 | 2020 |
