| High-performance mixed-precision linear solver for FPGAs J Sun, GD Peterson, OO Storaasli IEEE Transactions on Computers 57 (12), 1614-1623, 2008 | 96 | 2008 |
| Sparse matrix-vector multiplication design on FPGAs J Sun, G Peterson, O Storaasli 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines …, 2007 | 73 | 2007 |
| An FPGA implementation for solving least square problem D Yang, GD Peterson, H Li, J Sun 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines …, 2009 | 60 | 2009 |
| A high performance and memory efficient LU decomposer on FPGAs G Wu, Y Dou, J Sun, GD Peterson IEEE transactions on computers 61 (3), 366-378, 2010 | 48 | 2010 |
| Performance comparison of cholesky decomposition on GPUs and FPGAs D Yang, J Sun, J Lee, G Liang, DD Jenkins, GD Peterson, H Li Symposium on Application Accelerators in High Performance Computing 7, 35, 2010 | 35 | 2010 |
| An effective execution time approximation method for parallel computing J Sun, GD Peterson IEEE Transactions on Parallel and Distributed Systems 23 (11), 2024-2032, 2012 | 24 | 2012 |
| Robust stabilization over communication channels in the presence of unstructured uncertainty J Sun, SM Djouadi IEEE Transactions on Automatic Control 54 (4), 830-834, 2009 | 19 | 2009 |
| Method and apparatus for analyzing features or characteristics of a cable in a network J Sun, D Wu, H Nguyen US Patent 9,696,361, 2017 | 16 | 2017 |
| Mapping sparse matrix-vector multiplication on fpgas J Sun, G Peterson, O Storaasli Reconfigurable Systems Summer Institute (RSSI 2007), 1-10, 2007 | 16 | 2007 |
| SerDes architecture with a hidden backchannel protocol J Sun US Patent 10,212,260, 2019 | 13 | 2019 |
| Second-order clock recovery using three feedback paths Y Hidaka US Patent 10,892,763, 2021 | 10 | 2021 |
| Low power SerDes architecture and protocol J Sun, H Qian, LCF Cheng US Patent 10,069,660, 2018 | 10 | 2018 |
| Systems and methods to adaptively mitigate electro-magnetic interference (EMI) in automotive and industrial communication systems S Dai, KW Cheong, Z Gu, J Sun, X Wu US Patent 9,716,529, 2017 | 9 | 2017 |
| Serdes pre-equalizer having adaptable preset coefficient registers J Sun, H Qian US Patent 11,032,111, 2021 | 8 | 2021 |
| Method and apparatus for virtual cable test using echo canceller coefficients J Sun, D Wu, X Fang, B Chen, W Lo US Patent 8,582,443, 2013 | 8 | 2013 |
| Parallelizing sparse LU decomposition on FPGAs G Wu, X Xie, Y Dou, J Sun, D Wu, Y Li 2012 International Conference on Field-Programmable Technology, 352-359, 2012 | 8 | 2012 |
| Systems and methods to mitigate electro-magnetic interference in single twisted-pair-based communication systems S Dai, KW Cheong, Z Gu, J Sun, M Zeng, X Wu US Patent 9,838,072, 2017 | 7 | 2017 |
| High performance reconfigurable computing for linear algebra: design and performance analysis J Sun | 6 | 2008 |
| Eye monitor for parallelized digital equalizers J Sun, H Qian US Patent 10,992,501, 2021 | 5 | 2021 |
| Method and apparatus for signal detection and baseline wander cancellation J Sun US Patent 9,485,120, 2016 | 5 | 2016 |
Gregory D. PetersonUniversity of TennesseeVerified email at utk.edu
