| A Monte Carlo approach for maximum power estimation based on extreme value theory NE Evmorfopoulos, GI Stamoulis, JN Avaritsiotis IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002 | 58 | 2002 |
| An adaptive digital fuzzy architecture for application-specific integrated circuits NE Evmorfopoulos, JN Avaritsiotis Active and passive electronic components 25, 289-306, 2002 | 23 | 2002 |
| Precise identification of the worst-case voltage drop conditions in power grid verification N Evmorfopoulos, D Karampatzakis, G Stamoulis Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 21 | 2006 |
| Analytical modeling of transient electromigration stress based on boundary reflections MA Al Shohel, VA Chhabria, N Evmorfopoulos, SS Sapatnekar 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-8, 2021 | 18 | 2021 |
| Accurate estimation of dynamic timing slacks using event-driven simulation D Garyfallou, I Tsiokanos, N Evmorfopoulos, G Stamoulis, ... 2020 21st International Symposium on Quality Electronic Design (ISQED), 225-230, 2020 | 18 | 2020 |
| Gate delay estimation with library compatible current source models and effective capacitance D Garyfallou, S Simoglou, N Sketopoulos, C Antoniadis, CP Sotiriou, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (5), 962-972, 2021 | 15 | 2021 |
| A placement-aware soft error rate estimation of combinational circuits for multiple transient faults in CMOS technology GI Paliaroutis, P Tsoumanis, N Evmorfopoulos, G Dimitriou, GI Stamoulis 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2018 | 15 | 2018 |
| Large-scale power grid analysis on parallel architectures K Daloukas, N Evmorfopoulos, P Tsompanopoulou, G Stamoulis US Patent 9,858,369, 2018 | 15 | 2018 |
| Fast transform-based preconditioners for large-scale power grid analysis on massively parallel architectures K Daloukas, N Evmorfopoulos, G Drasidis, M Tsiampas, ... Proceedings of the International Conference on Computer-Aided Design, 384-391, 2012 | 15 | 2012 |
| System and method for determining simulated response extrema for integrated circuit power supply networks G Stamoulis, S Bantas, D Bountas, N Evmorfopoulos, M Tsiampas, ... US Patent 8,516,423, 2013 | 14 | 2013 |
| A layout-based soft error rate estimation and mitigation in the presence of multiple transient faults in combinational logic C Georgakidis, GI Paliaroutis, N Sketopoulos, P Tsoumanis, C Sotiriou, ... 2020 21st International Symposium on Quality Electronic Design (ISQED), 231-236, 2020 | 13 | 2020 |
| Parallel fast transform-based preconditioners for large-scale power grid analysis on graphics processing units (gpus) K Daloukas, N Evmorfopoulos, P Tsompanopoulou, G Stamoulis IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 12 | 2016 |
| Fast and accurate BER estimation methodology for I/O links based on extreme value theory A Cevrero, N Evmorfopoulos, C Antoniadis, P Ienne, Y Leblebici, A Burg, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 503-508, 2013 | 10 | 2013 |
| Exploiting extended krylov subspace for the reduction of regular and singular circuit models C Chatzigeorgiou, D Garyfallou, G Floros, N Evmorfopoulos, G Stamoulis Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 9 | 2021 |
| Set pulse characterization and ser estimation in combinational logic with placement and multiple transient faults considerations GI Paliaroutis, P Tsoumanis, N Evmorfopoulos, G Dimitriou, GI Stamoulis Technologies 8 (1), 5, 2020 | 9 | 2020 |
| Efficient IC hotspot thermal analysis via low-rank Model Order Reduction G Floros, N Evmorfopoulos, G Stamoulis Integration 66, 1-8, 2019 | 9 | 2019 |
| Efficient sparsification of dense circuit matrices in model order reduction C Antoniadis, N Evmorfopoulos, G Stamoulis Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 9 | 2019 |
| EVT-based worst case delay estimation under process variation C Antoniadis, D Garyfallou, N Evmorfopoulos, G Stamoulis 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 9 | 2018 |
| Accelerating electromigration stress analysis using low-rank balanced truncation O Axelou, G Floros, N Evmorfopoulos, G Stamoulis 2022 18th International Conference on Synthesis, Modeling, Analysis and …, 2022 | 8 | 2022 |
| A sparsity-aware MOR methodology for fast and accurate timing analysis of VLSI interconnects D Garyfallou, C Antoniadis, N Evmorfopoulos, G Stamoulis 2019 16th International Conference on Synthesis, Modeling, Analysis and …, 2019 | 8 | 2019 |
