| Minimalist open-page: A DRAM page-mode scheduling policy for the many-core era D Kaseridis, J Stuecheli, LK John Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 201 | 2011 |
| The virtual write queue: Coordinating DRAM and last-level cache policies J Stuecheli, D Kaseridis, D Daly, HC Hunter, LK John ACM SIGARCH Computer Architecture News 38 (3), 72-82, 2010 | 167 | 2010 |
| Elastic refresh: Techniques to mitigate refresh penalties in high density memory J Stuecheli, D Kaseridis, HC Hunter, LK John 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 375-384, 2010 | 149 | 2010 |
| System-level max power (SYMPO) a systematic approach for escalating system-level power consumption using synthetic benchmarks K Ganesan, J Jo, WL Bircher, D Kaseridis, Z Yu, LK John Proceedings of the 19th international conference on Parallel architectures …, 2010 | 67 | 2010 |
| Modeling program resource demand using inherent program characteristics J Chen, LK John, D Kaseridis ACM SIGMETRICS Performance Evaluation Review 39 (1), 1-12, 2011 | 63 | 2011 |
| Bank-aware dynamic cache partitioning for multicore architectures D Kaseridis, J Stuecheli, LK John 2009 International Conference on Parallel Processing, 18-25, 2009 | 52 | 2009 |
| A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large cmp systems D Kaseridis, J Stuecheli, J Chen, LK John HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010 | 43 | 2010 |
| Cache friendliness-aware managementof shared last-level caches for highperformance multi-core systems D Kaseridis, MF Iqbal, LK John IEEE transactions on computers 63 (4), 874-887, 2013 | 30 | 2013 |
| Reseeding-based test set embedding with reduced test sequences E Kalligeros, D Kaseridis, X Kavousianos, D Nikolos Sixth international symposium on quality electronic design (isqed'05), 226-231, 2005 | 27 | 2005 |
| An efficient test set embedding scheme with reduced test data storage and test sequence length requirements for scan-based testing D Kaseridis, E Kalligeros, X Kavousianos, D Nikolos Inf. Pap. Dig. IEEE ETS, 147-150, 2005 | 12 | 2005 |
| Coordinating DRAM and last-level-cache policies with the virtual write queue J Stuecheli, D Kaseridis, D Daly, H Hunter, L John IEEE micro 31 (1), 90-98, 2010 | 8 | 2010 |
| Mcfq: Leveraging memory-level parallelism and application's cache friendliness for efficient management of quasi-partitioned last-level caches D Kaseridis, MF Iqbal, J Stuecheli, LK John 2011 International Conference on Parallel Architectures and Compilation …, 2011 | 4 | 2011 |
| System-level max power (SYMPO) K Ganesan, J Jo, WL Bircher, D Kaseridis, Z Yu, LK John Proceedings of the 19th international conference on Parallel architectures …, 2010 | 3 | 2010 |
| CMP/CMT Scaling of SPECjbb2005 on UltraSPARC T1 D Kaseridis, LK John Workshop on Computer Architecture Evaluation using Commercial Workloads, 2007 | 3 | 2007 |
| John." System-level Max Power (SYMPO)-A systematic approach for escalating system-level power consumption using synthetic benchmarks." K Ganesan, J Jo, WL Bircher, D Kaseridis, Z Yu Parallel Architectures and Compilation Techniques (PACT), 2010 19th …, 0 | 3 | |
| Optimized streaming in an un-ordered interconnect AK Tummala, J Jalal, PG Meyer, D Kaseridis US Patent 10,423,466, 2019 | 2 | 2019 |
| Cache friendliness-aware management of shared last-level caches for high performance multi-core systems. Computers D Kaseridis, M Iqbal, L John IEEE Transactions on, 2013 | 2 | 2013 |
| An apparatus and method for handling memory access requests J Jalal, G Ramagiri, TP Ringe, MD Werkheiser, AK Tummala, D Kaseridis US Patent App. 18/000,761, 2023 | | 2023 |
| Data processing network with flow compaction for streaming data transfer J Jalal, TP Ringe, PK Mannava, D Kaseridis US Patent 11,483,260, 2022 | | 2022 |
| Cache retention data management AJ Waugh, D Kaseridis, KM Bruce, M Filippo, JM Pusdesris, J Jalal US Patent 11,200,177, 2021 | | 2021 |
Lizy Kurian JohnTruchard Foundation Chair and Professor at UT Austin ECEΗ διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα ece.utexas.edu
