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Haridimos T. Vergos
Haridimos T. Vergos
Professor, Computer Engineering & Informatics Dept, University of Patras
Verified email at ceid.upatras.gr - Homepage
Title
Cited by
Cited by
Year
High-speed parallel-prefix modulo adders
L Kalampoukas, D Nikolos, C Efstathiou, HT Vergos, J Kalamatianos
IEEE Transactions on Computers 49 (7), 673-680, 2000
2012000
Diminished-one modulo adder design
HT Vergos, C Efstathiou, D Nikolos
IEEE Transactions on Computers 51 (12), 1389-1399, 2002
1962002
Fast parallel-prefix modulo adders
C Efstathiou, HT Vergos, D Nikolos
IEEE Transactions on Computers 53 (9), 1211-1216, 2004
1262004
Efficient diminished-1 modulo multipliers
C Efstathiou, HT Vergos, G Dimitrakopoulos, D Nikolos
IEEE Transactions on Computers 54 (4), 491-496, 2005
962005
Modified Booth modulo multipliers
C Efstathiou, HT Vergos, D Nikolos
IEEE Transactions on Computers 53 (3), 370-374, 2004
912004
Design of efficient modulo multipliers
HT Vergos, C Efstathiou
IET Computers & Digital Techniques 1 (1), 49-57, 2007
832007
On Modulo Adder Design
HT Vergos, G Dimitrakopoulos
IEEE Transactions on Computers 61 (2), 173-186, 2010
812010
Modulo adder design using select-prefix blocks
C Efstathiou, HT Vergos, D Nikolos
IEEE Transactions on Computers 52 (11), 1399-1406, 2003
812003
A Unifying Approach for Weighted and Diminished-1 Modulo Addition
HT Vergos, C Efstathiou
IEEE Transactions on Circuits and Systems II: Express Briefs 55 (10), 1041-1045, 2008
652008
New architectures for modulo adders
G Dimitrakopoulos, DG Nikolos, HT Vergos, D Nikolos, C Efstathiou
2005 12th IEEE International Conference on Electronics, Circuits and Systems …, 2005
482005
Efficient modulo adder architectures
HT Vergos, C Efstathiou
Integration, the VLSI Journal 42 (2), 149-157, 2009
372009
Handling zero in diminished-one modulo adders
C Efstathiou, HT Vergos, D Nikolos
International journal of electronics 90 (2), 133-144, 2003
352003
Performance recovery in direct-mapped faulty caches via the use of a very small fully associative spare cache
HT Vergos, D Nikolos
Proceedings of 1995 IEEE International Computer Performance and …, 1995
271995
On the design of modulo subtractors and adders/subtractors
E Vassalos, D Bakalis, HT Vergos
Circuits, Systems, and Signal Processing 30 (6), 1445-1461, 2011
212011
Diminished-1 modulo squarer design
HT Vergos, C Efstathiou
IEE Proceedings-Computers and Digital Techniques 152 (5), 561-566, 2005
212005
Efficient fault tolerant cache memory design
HT Vergos, D Nikolos
Microprocessing and microprogramming 41 (2), 153-169, 1995
211995
RNS assisted image filtering and edge detection
E Vassalos, D Bakalis, HT Vergos
2013 18th International Conference on Digital Signal Processing (DSP), 1-6, 2013
192013
A family of parallel-prefix modulo adders
G Dimitrakopoulos, HT Vergos, D Nikolos, C Efstathiou
Proceedings IEEE International Conference on Application-Specific Systems …, 2003
192003
Modified Booth 1's complement and modulo multipliers
C Efstathiou, HT Vergos
ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and …, 2000
192000
Fast modulo multi-operand adders and residue generators
HT Vergos, D Bakalis, C Efstathiou
Integration 43 (1), 42-48, 2010
182010
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