| A practical automatic polyhedral parallelizer and locality optimizer U Bondhugula, A Hartono, J Ramanujam, P Sadayappan ACM SIGPLAN conference on Programming Languages Design and Implementation 43 …, 2008 | 1540* | 2008 |
| Mlir: Scaling compiler infrastructure for domain specific computation C Lattner, M Amini, U Bondhugula, A Cohen, A Davis, J Pienaar, R Riddle, ... 2021 IEEE/ACM International Symposium on Code Generation and Optimization …, 2021 | 459 | 2021 |
| Automatic transformations for communication-minimized parallelization and locality optimization in the polyhedral model U Bondhugula, M Baskaran, S Krishnamoorthy, J Ramanujam, A Rountev, ... International Conference on Compiler Construction, 132-146, 2008 | 455 | 2008 |
| Effective automatic parallelization of stencil computations S Krishnamoorthy, M Baskaran, U Bondhugula, J Ramanujam, A Rountev, ... ACM SIGPLAN conference on Programming Language Design and Implementation …, 2007 | 320 | 2007 |
| MLIR: A Compiler Infrastructure for the End of Moore's Law C Lattner, M Amini, U Bondhugula, A Cohen, A Davis, J Pienaar, R Riddle, ... arXiv preprint arXiv:2002.11054, 2020 | 307 | 2020 |
| A compiler framework for optimization of affine loop nests for GPGPUs MM Baskaran, U Bondhugula, S Krishnamoorthy, J Ramanujam, ... Proceedings of the 22nd annual international conference on Supercomputing …, 2008 | 306 | 2008 |
| Polymage: Automatic optimization for image processing pipelines RT Mullapudi, V Vasista, U Bondhugula International conference on Architectural Support for Programming Languages …, 2015 | 274 | 2015 |
| Tiling stencil computations to maximize parallelism V Bandishti, I Pananilath, U Bondhugula SC'12: Proceedings of the International Conference on High Performance …, 2012 | 247 | 2012 |
| Loop transformations: convexity, pruning and optimization LN Pouchet, U Bondhugula, C Bastoul, A Cohen, J Ramanujam, ... ACM SIGPLAN Notices 46 (1), 549-562, 2011 | 185 | 2011 |
| Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories MM Baskaran, U Bondhugula, S Krishnamoorthy, J Ramanujam, ... Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of …, 2008 | 160 | 2008 |
| Compiling affine loop nests for distributed-memory parallel architectures U Bondhugula Proceedings of the International Conference on High Performance Computing …, 2013 | 149* | 2013 |
| Combined iterative and model-driven optimization in an automatic parallelization framework LN Pouchet, U Bondhugula, C Bastoul, A Cohen, J Ramanujam, ... SC'10: Proceedings of the 2010 ACM/IEEE International Conference for High …, 2010 | 120* | 2010 |
| Data layout transformation for enhancing data locality on NUCA chip multiprocessors Q Lu, C Alias, U Bondhugula, T Henretty, S Krishnamoorthy, ... Parallel Architectures and Compilation Techniques, 2009. PACT'09. 18th …, 2009 | 108 | 2009 |
| A model for fusion and code motion in an automatic parallelizing compiler U Bondhugula, O Gunluk, S Dash, L Renganarayanan Proceedings of the 19th international conference on Parallel architectures …, 2010 | 92 | 2010 |
| Parallel FPGA-based all-pairs shortest-paths in a directed graph U Bondhugula, A Devulapalli, J Fernando, P Wyckoff, P Sadayappan Proceedings 20th IEEE International Parallel & Distributed Processing …, 2006 | 90 | 2006 |
| Diamond tiling: Tiling techniques to maximize parallelism for stencil computations U Bondhugula, V Bandishti, I Pananilath IEEE Transactions on Parallel and Distributed Systems 28 (5), 1285-1298, 2016 | 86 | 2016 |
| Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors MM Baskaran, N Vydyanathan, UKR Bondhugula, J Ramanujam, ... ACM sigplan notices 44 (4), 219-228, 2009 | 86 | 2009 |
| The Pluto+ algorithm: A practical approach for parallelization and locality optimization of affine loop nests U Bondhugula, A Acharya, A Cohen ACM Transactions on Programming Languages and Systems (TOPLAS) 38 (3), 12, 2016 | 76 | 2016 |
| A DSL compiler for accelerating image processing pipelines on FPGAs N Chugh, V Vasista, S Purini, U Bondhugula Proceedings of the 2016 International Conference on Parallel Architectures …, 2016 | 74 | 2016 |
| Generating efficient data movement code for heterogeneous architectures with distributed-memory R Dathathri, C Reddy, T Ramashekar, U Bondhugula Proceedings of the 22nd international conference on Parallel architectures …, 2013 | 69 | 2013 |
Albert CohenGoogleVerified email at google.com
