| Near-optimal worst-case throughput routing for two-dimensional mesh networks D Seo, A Ali, WT Lim, N Rafique 32nd International Symposium on Computer Architecture (ISCA'05), 432-443, 2005 | 282 | 2005 |
| SparTen: A sparse tensor accelerator for convolutional neural networks A Gondimalla, N Chesnut, M Thottethodi, TN Vijaykumar Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 281 | 2019 |
| Architectural support for operating system-driven CMP cache management N Rafique, WT Lim, M Thottethodi Proceedings of the 15th international conference on Parallel architectures …, 2006 | 267 | 2006 |
| Recursive array layouts and fast parallel matrix multiplication S Chatterjee, AR Lebeck, PK Patnala, M Thottethodi Proceedings of the eleventh annual ACM symposium on Parallel algorithms and …, 1999 | 243 | 1999 |
| Nonlinear array layouts for hierarchical memory systems S Chatterjee, VV Jain, AR Lebeck, S Mundhra, M Thottethodi Proceedings of the 13th international conference on Supercomputing, 444-453, 1999 | 216 | 1999 |
| Self-tuned congestion control for multiprocessor networks M Thottethodi, AR Lebeck, SS Mukherjee Proceedings HPCA Seventh International Symposium on High-Performance …, 2001 | 183 | 2001 |
| Effective management of DRAM bandwidth in multicore processors N Rafique, WT Lim, M Thottethodi 16th International Conference on Parallel Architecture and Compilation …, 2007 | 178 | 2007 |
| Newton: A DRAM-maker˘s accelerator-in-memory (AiM) architecture for machine learning M He, C Song, I Kim, C Jeong, S Kim, I Park, M Thottethodi, ... 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 163 | 2020 |
| SieveStore: a highly-selective, ensemble-level disk cache for cost-performance T Pritchett, M Thottethodi Proceedings of the 37th annual international symposium on Computer …, 2010 | 163 | 2010 |
| Puma: Purdue mapreduce benchmarks suite F Ahmad, S Lee, M Thottethodi, TN Vijaykumar | 146 | 2012 |
| A mostly-clean DRAM cache for effective hit speculation and self-balancing dispatch J Sim, GH Loh, H Kim, M OConnor, M Thottethodi 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 247-257, 2012 | 130 | 2012 |
| Tuning Strassen's matrix multiplication for memory efficiency M Thottethodi, S Chatterjee, AR Lebeck SC'98: Proceedings of the 1998 ACM/IEEE Conference on Supercomputing, 36-36, 1998 | 115* | 1998 |
| Dynamically configuring regions of a main memory in a write-back mode or a write-through mode J Sim, MS Thottethodi, GH Loh US Patent 9,552,294, 2017 | 109 | 2017 |
| Understanding and mitigating the impact of load imbalance in the memory caching tier YJ Hong, M Thottethodi Proceedings of the 4th annual Symposium on Cloud Computing, 1-17, 2013 | 89 | 2013 |
| MapReduce with communication overlap (MaRCO) F Ahmad, S Lee, M Thottethodi, TN Vijaykumar Journal of Parallel and Distributed Computing 73 (5), 608-620, 2013 | 89 | 2013 |
| Dynamic server provisioning to minimize cost in an IaaS cloud YJ Hong, J Xue, M Thottethodi Proceedings of the ACM SIGMETRICS joint international conference on …, 2011 | 89 | 2011 |
| Adaptive flow control for robust performance and energy SAR Jafri, YJ Hong, M Thottethodi, TN Vijaykumar 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 433-444, 2010 | 78 | 2010 |
| Aquacore: a programmable architecture for microfluidics AM Amin, M Thottethodi, TN Vijaykumar, S Wereley, SC Jacobson ACM SIGARCH Computer Architecture News 35 (2), 254-265, 2007 | 58 | 2007 |
| Exploiting global knowledge to achieve self-tuned congestion control for k-ary n-cube networks M Thottethodi, AR Lebeck, SS Mukherjee IEEE Transactions on Parallel and Distributed Systems 15 (3), 257-272, 2004 | 56 | 2004 |
| Die-stacked device with partitioned multi-hop network MS Thottethodi, GH Loh US Patent 9,065,722, 2015 | 55 | 2015 |
T. N. VijaykumarProfessor of ECE, PurdueVerified email at ecn.purdue.edu
