| Towards 10000TOPS/W DNN inference with analog in-memory computing–a circuit blueprint, device options and requirements S Cosemans, B Verhoef, J Doevenspeck, IA Papistas, F Catthoor, ... 2019 IEEE International Electron Devices Meeting (IEDM), 22.2. 1-22.2. 4, 2019 | 63 | 2019 |
| SOT-MRAM based analog in-memory computing for DNN inference J Doevenspeck, K Garello, B Verhoef, R Degraeve, S Van Beek, D Crotti, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 58 | 2020 |
| Diana: An end-to-end energy-efficient digital and analog hybrid neural network soc K Ueyoshi, IA Papistas, P Houshmand, GM Sarda, V Jain, M Shi, Q Zheng, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 47 | 2022 |
| A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration IA Papistas, S Cosemans, B Rooseleer, J Doevenspeck, MH Na, A Mallik, ... 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021 | 36 | 2021 |
| Diana: An end-to-end hybrid digital and analog neural network soc for the edge P Houshmand, GM Sarda, V Jain, K Ueyoshi, IA Papistas, M Shi, Q Zheng, ... IEEE Journal of Solid-State Circuits 58 (1), 203-215, 2022 | 29 | 2022 |
| Opportunities and limitations of emerging analog in-memory compute DNN architectures P Houshmand, S Cosemans, L Mei, I Papistas, D Bhattacharjee, ... 2020 IEEE International Electron Devices Meeting (IEDM), 29.1. 1-29.1. 4, 2020 | 23 | 2020 |
| Fq-conv: Fully quantized convolution for efficient and accurate inference BE Verhoef, N Laubeuf, S Cosemans, P Debacker, I Papistas, A Mallik, ... arXiv preprint arXiv:1912.09356, 2019 | 20 | 2019 |
| Bandwidth-to-area comparison of through silicon vias and inductive links for 3-D ICs IA Papistas, VF Pavlidis 2015 European Conference on Circuit Theory and Design (ECCTD), 1-4, 2015 | 16 | 2015 |
| IGZO-based compute cell for analog in-memory computing—DTCO analysis to enable ultralow-power AI at edge D Saito, J Doevenspeck, S Cosemans, H Oh, M Perumkunnil, IA Papistas, ... IEEE Transactions on Electron Devices 67 (11), 4616-4620, 2020 | 14 | 2020 |
| Design-technology space exploration for energy efficient AiMC-based inference acceleration D Bhattacharjee, N Laubeuf, S Cosemans, I Papistas, A Maliik, ... 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 10 | 2021 |
| Contactless heterogeneous 3-D ICs for smart sensing systems IA Papistas, VF Pavlidis Integration 62, 329-340, 2018 | 10 | 2018 |
| Charge sharing and charge injection A/D converters for analog in-memory computing M Caselli, IA Papistas, S Cosemans, A Mallik, P Debacker, D Verkest 2021 19th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2021 | 8 | 2021 |
| Fabrication cost analysis for contactless 3-D ICs IA Papistas, VF Pavlidis, D Velenis IEEE Transactions on Circuits and Systems II: Express Briefs 66 (5), 758-762, 2019 | 8 | 2019 |
| Efficient Modeling of Crosstalk Noise on Power Distribution Networks for Contactless 3-D ICs IA Papistas, VF Pavlidis IEEE Transactions on Circuits and Systems I: Regular Papers, 2018 | 8 | 2018 |
| Contactless inter-tier communication for heterogeneous 3-D ICs IA Papistas, VF Pavlidis 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 6 | 2017 |
| Dynamic quantization range control for analog-in-memory neural networks acceleration N Laubeuf, J Doevenspeck, IA Papistas, M Caselli, S Cosemans, ... ACM Transactions on Design Automation of Electronic Systems (TODAES) 27 (5 …, 2022 | 5 | 2022 |
| Crosstalk noise effects of on-chip inductive links on power delivery networks IA Papistas, VF Pavlidis 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1938-1941, 2016 | 5 | 2016 |
| Inter-tier crosstalk noise on power delivery networks for 3-D ICs with inductively-coupled interconnects IA Papistas, VF Pavlidis Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 257-262, 2016 | 4 | 2016 |
| Cost modeling and analysis of TSV and contactless 3D-ICs M Jiang, IA Papistas, VF Pavlidis Proceedings of the 2020 on Great Lakes Symposium on VLSI, 519-524, 2020 | 3 | 2020 |
| Novel memory devices tailored to analog in-memory computing for neural network inference S Cosemans, J Doevenspeck, B Verhoef, I Papistas, N Laubeuf, ... | 1 | 2020 |
Peter DebackerTechnical Expert, easicsVerified email at easics.be
