Alberto Bosio

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	All	Since 2019
Citations	2942	1592
h-index	26	19
i10-index	98	55

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Patrick GirardLIRMMVerified email at lirmm.fr
Arnaud VirazelLIRMM - Univ. Montpellier / CNRSVerified email at lirmm.fr
Luigi DililloIES, CNRS, University of MontpellierVerified email at umontpellier.fr
Aida Todri-SanialFull Professor, TU Eindhoven | Director of Research, CNRSVerified email at tue.nl
Giorgio Di NataleCNRS - TIMAVerified email at univ-grenoble-alpes.fr
Marcello TraiolaTenured Research Scientist - Inria Rennes / IRISA labVerified email at inria.fr
Stefano Di CarloFull Professor, Politecnico di TorinoVerified email at polito.it
Ian O'ConnorEcole Centrale de LyonVerified email at ec-lyon.fr
Ernesto SanchezAssociate Professor at Politecnico di TorinoVerified email at polito.it
Mario BarbareschiTenured Assistant Professor | Dipartimento di Ingegneria Elettrica e delle Tecnologie dellVerified email at unina.it
Georgios TsiligiannisIES - University of MontpellierVerified email at ies.univ-montp2.fr
Alessandro SavinoPolitecnico di Torino, DAUINVerified email at polito.it
paolo bernardiPolitecnico di TorinoVerified email at polito.it
Nabil BadereddineIntel CorporationVerified email at intel.com
Annachiara RuospoAssistant Professor (RTD-A) at Politecnico di TorinoVerified email at polito.it
Gennaro Severino RodriguesPh.D., UFRGSVerified email at inf.ufrgs.br
Matteo SONZA REORDAPolitecnico di Torino, Dept. of Control and Computer EngineeringVerified email at polito.it
Alfredo BensoPolitecnico di Torino - Systems Biology GroupVerified email at polito.it
Fernanda Lima KastensmidtProfessor de Ciência da Computação, Universidade Federal do Rio Grande do SulVerified email at inf.ufrgs.br
Paolo PRINETTOProfessor of Computer Engineering, Politecnico di Torino, Torino (Italy)Verified email at polito.it

Alberto Bosio

Full Professor, Ecole Centrale de Lyon, Institute of Nanotechnology

Verified email at ec-lyon.fr - Homepage

Computer Engineer Approximate Computing Emerging Technologies Design and Test of digital Circuits


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A study of tapered 3-D TSVs for power and thermal integrity A Todri, S Kundu, P Girard, A Bosio, L Dilillo, A Virazel IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (2), 306-319, 2012	88	2012
Advanced test methods for SRAMs: effective solutions for dynamic fault detection in nanoscaled technologies A Bosio, L Dilillo, P Girard, S Pravossoudovitch, A Virazel Springer Science & Business Media, 2009	84	2009
A reliability analysis of a deep neural network A Bosio, P Bernardi, A Ruospo, E Sanchez 2019 IEEE Latin American Test Symposium (LATS), 1-6, 2019	81	2019
Using TMR architectures for yield improvement J Vial, A Bosio, P Girard, C Landrault, S Pravossoudovitch, A Virazel 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI …, 2008	78	2008
Multiple cell upset classification in commercial SRAMs G Tsiligiannis, L Dilillo, A Bosio, P Girard, S Pravossoudovitch, A Todri, ... IEEE Transactions on Nuclear Science 61 (4), 1747-1754, 2014	68	2014
Lifting: A flexible open-source fault simulator A Bosio, G Di Natale 2008 17th Asian Test Symposium, 35-40, 2008	67	2008
March AB, March AB1: new March tests for unlinked dynamic memory faults A Benso, A Bosio, S Di Carlo, G Di Natale, P Prinetto IEEE International Conference on Test, 2005., 8 pp.-841, 2005	51	2005
Statistical reliability estimation of microprocessor-based systems A Savino, S Di Carlo, G Politano, A Benso, A Bosio, G Di Natale IEEE Transactions on Computers 61 (11), 1521-1534, 2011	50	2011
Testing a commercial MRAM under neutron and alpha radiation in dynamic mode G Tsiligiannis, L Dilillo, A Bosio, P Girard, A Todri, A Virazel, SS McClure, ... IEEE Transactions on Nuclear Science 60 (4), 2617-2622, 2013	49	2013
A functional verification based fault injection environment A Benso, A Bosio, S Di Carlo, R Mariani 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007	44	2007
Derric: A tool for unified logic diagnosis A Rousset, A Bosio, P Girard, C Landrault, S Pravossoudovitch, A Virazel 12th IEEE European Test Symposium (ETS'07), 13-20, 2007	43	2007
Dynamic test methods for COTS SRAMs G Tsiligiannis, L Dilillo, V Gupta, A Bosio, P Girard, A Virazel, H Puchner, ... IEEE Transactions on Nuclear Science 61 (6), 3095-3102, 2014	38	2014
Survey on approximate computing and its intrinsic fault tolerance G Rodrigues, F Lima Kastensmidt, A Bosio Electronics 9 (4), 557, 2020	37	2020
Syra: Early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems A Vallero, A Savino, A Chatzidimitriou, M Kaliorakis, M Kooli, M Riera, ... IEEE Transactions on Computers 68 (5), 765-783, 2018	37	2018
Evaluating convolutional neural networks reliability depending on their data representation A Ruospo, A Bosio, A Ianne, E Sanchez 2020 23rd Euromicro Conference on Digital System Design (DSD), 672-679, 2020	36	2020
Cross-layer system reliability assessment framework for hardware faults A Vallero, A Savino, G Politano, S Di Carlo, A Chatzidimitriou, S Tselonis, ... 2016 IEEE International Test Conference (ITC), 1-10, 2016	35	2016
Automatic March tests generation for static and dynamic faults in SRAMs A Benso, A Bosio, S Di Carlo, G Di Natale, P Prinetto European Test Symposium (ETS'05), 122-127, 2005	35	2005
Investigating data representation for efficient and reliable convolutional neural networks A Ruospo, E Sanchez, M Traiola, I O’connor, A Bosio Microprocessors and Microsystems 86, 104318, 2021	34	2021
A functional power evaluation flow for defining test power limits during at-speed delay testing M Valka, A Bosio, L Dilillo, P Girard, S Pravossoudovitch, A Virazel, ... 2011 Sixteenth IEEE European Test Symposium, 153-158, 2011	33	2011
A pipelined multi-level fault injector for deep neural networks A Ruospo, A Balaara, A Bosio, E Sanchez 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2020	31	2020

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