| Analytical heat transfer model for thermal through-silicon vias H Xu, VF Pavlidis, G De Micheli 2011 Design, Automation & Test in Europe, 1-6, 2011 | 51 | 2011 |
| Effect of process variations in 3D global clock distribution networks H Xu, VF Pavlidis, G De Micheli ACM Journal on Emerging Technologies in Computing Systems (JETC) 8 (3), 1-25, 2012 | 20 | 2012 |
| The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter H Xu, VF Pavlidis, W Burleson, G De Micheli International Symposium on Quality Electronic Design (ISQED), 320 - 327, 2012 | 19 | 2012 |
| Process-induced skew variation for scaled 2-D and 3-D ICs H Xu, VF Pavlidis, G De Micheli Proceedings of the 12th ACM/IEEE international workshop on System level …, 2010 | 13 | 2010 |
| Timing uncertainty in 3-D clock trees due to process variations and power supply noise H Xu, VF Pavlidis, X Tang, W Burleson, G De Micheli IEEE transactions on very large scale integration (VLSI) systems 21 (12 …, 2013 | 12 | 2013 |
| A fast incremental clock skew scheduling algorithm for slack optimization K Wang, H Fang, H Xu, X Cheng 2008 Asia and South Pacific Design Automation Conference, 492-497, 2008 | 7 | 2008 |
| Skew variability in 3-D ICs with multiple clock domains H Xu, VF Pavlidis, G De Micheli 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2221-2224, 2011 | 6 | 2011 |
| An accurate dynamic power model on FPGA routing resources X Tang, L Wang, H Xu 2012 IEEE 11th International Conference on Solid-State and Integrated …, 2012 | 3 | 2012 |
| Repeater insertion for two-terminal nets in three-dimensional integrated circuits H Xu, VF Pavlidis, G De Micheli Nano-Net: 4th International ICST Conference, Nano-Net 2009, Lucerne …, 2009 | 3 | 2009 |
| Enhanced wafer matching heuristics for 3-D ICs VF Pavlidis, H Xu, G De Micheli 2012 17th IEEE European Test Symposium (ETS), 1-1, 2012 | 2 | 2012 |
| Modeling and Design Techniques for 3-D ICs under Process, Voltage, and Temperature Variations H Xu EPFL, 2012 | 2 | 2012 |
| Synchronization and power integrity issues in 3-D ICs VF Pavlidis, H Xu, I Tsioutsios, G De Micheli 2010 IEEE Asia Pacific Conference on Circuits and Systems, 536-539, 2010 | 2 | 2010 |
| Power-Aware Gated Clock Routing with Merging Cost Backward Annotation Using Simulated Annealing Method D Lian, H Xu, K Wang, X Cheng Acta Scientiarum Naturalium Universitatis Pekinensis 43 (5), 694-702, 2007 | 1* | 2007 |
| Repeater Insertion Techniques for 3D Interconnects H Xu, V Pavlidis, G De Micheli Design, Automation, and Test Conference in Europe - 3D Integration Workshop …, 2010 | | 2010 |
| 面向新型北大众志系统芯片的约束设置与逻辑综合 许浒 Peking University, 北京大学, 2008 | | 2008 |
| 给定偏差约束下的时钟布线局部拓扑构造优化算法 段炼， 许浒， 王逵， 程旭 计算机辅助设计与图形学学报 20 (4), 452-458, 2008 | | 2008 |
| LSI1 A Nakhjavani, N Sattar Aliakbari, LG Amarù, F Angiolini, JL Ayala Rodrigo, ... | | |
| LSI2 N Aliakbari, C Baj-Rossi, G Beanato, SK Bobba, C Boero, C Burget, ... | | |
Giovanni De MicheliEPFL, StanfordVerified email at epfl.ch
