VINAYAKA JYOTHI
VINAYAKA JYOTHI
NYU Tandon School of Engineering
Verified email at nyu.edu - Homepage
Title
Cited by
Cited by
Year
Design and analysis of ring oscillator based Design-for-Trust technique
J Rajendran, V Jyothi, O Sinanoglu, R Karri
29th VLSI Test Symposium, 105-110, 2011
832011
Blue team red team approach to hardware trust assessment
J Rajendran, V Jyothi, R Karri
2011 IEEE 29th international conference on computer design (ICCD), 285-288, 2011
342011
Brain: Behavior based adaptive intrusion detection in networks: Using hardware performance counters to detect ddos attacks
V Jyothi, X Wang, SK Addepalli, R Karri
2016 29th International Conference on VLSI Design and 2016 15th …, 2016
322016
FPGA Trust Zone: Incorporating Trust and Reliability into FPGA Designs
RSRK Vinayaka Jyothi, Manasa Thoonoli
34th IEEE International Conference on Computer Design (ICCD), 2016
182016
Intra-die process variation aware anomaly detection in FPGAs
Y Pino, V Jyothi, M French
2014 International Test Conference, 1-6, 2014
152014
Ring oscillator based design-for-trust
V Jyothi, R Karri, J Rajendran, O Sinanoglu
US Patent 9,081,991, 2015
122015
Deep packet field extraction engine (DPFEE): A pre-processor for network intrusion detection and denial-of-service detection systems
V Jyothi, SK Addepalli, R Karri
2015 33rd IEEE International Conference on Computer Design (ICCD), 266-272, 2015
112015
TAINT: tool for automated INsertion of Trojans
V Jyothi, P Krishnamurthy, F Khorrami, R Karri
2017 IEEE International Conference on Computer Design (ICCD), 545-548, 2017
72017
DPFEE: A high performance scalable pre-processor for network security systems
V Jyothi, SK Addepalli, R Karri
IEEE Transactions on Multi-Scale Computing Systems 4 (1), 55-68, 2017
72017
System, method and computer-accessible medium for network intrusion detection
SK Addepalli, R Karri, V Jyothi
US Patent 10,735,438, 2020
62020
Hardware Trojan Attacks in FPGA and protection approaches
V Jyothi, JJV Rajendran
The Hardware Trojan War, 345-368, 2018
62018
Fingerprinting field programmable gate arrays
V Jyothi, A Poojari, R Stern, R Karri
2017 IEEE International Conference on Computer Design (ICCD), 337-340, 2017
42017
Secure and trusted multi-tenant service delivery platform for distributed multitenant-capable ai solution model compute processors
SK Addepalli, V Jyothi, AH Poojari
US Patent App. 16/789,371, 2020
2020
Real-time customizable ai model collaboration and marketplace service over a trusted ai model network
SK Addepalli, V Jyothi, AH Poojari
US Patent App. 16/789,357, 2020
2020
Systems and methods of security for trusted artificial intelligence hardware processing
SK Addepalli, V Jyothi, AH Poojari
US Patent App. 16/528,545, 2020
2020
Systems and methods for artificial intelligence with a flexible hardware processing framework
SK Addepalli, V Jyothi, AH Poojari
US Patent App. 16/528,548, 2020
2020
Systems and methods for continuous & real-time ai adaptive sense learning
SK Addepalli, V Jyothi, AH Poojari
US Patent App. 16/528,549, 2020
2020
Systems and methods for artificial intelligence hardware processing
SK Addepalli, V Jyothi, AH Poojari
US Patent App. 16/528,543, 2020
2020
Lightweight, highspeed and energy efficient asynchronous and file system-based ai processing interface framework
SK Addepalli, V Jyothi, AH Poojari
US Patent App. 16/528,551, 2020
2020
SYSTEMS AND METHODS FOR POWER MANAGEMENT OF HARDWARE UTILIZING VIRTUAL MULTILANE ARCHITECTURE
S Kumar Addepalli, V Jyothi, AH Poojari
US Patent App. 16/528,553, 2020
2020
The system can't perform the operation now. Try again later.
Articles 1–20