Wenjing Rao
Cited by
Cited by
Test application time and volume compression through seed overlapping
W Rao, I Bayraktaroglu, A Orailoglu
Proceedings 2003. Design Automation Conference (IEEE Cat. No. 03CH37451 …, 2003
Logic mapping in crossbar-based nanoarchitectures
W Rao, A Orailoglu, R Karri
IEEE Design & Test of Computers 26 (1), 68-77, 2009
Topology aware mapping of logic functions onto nanowire-based crossbar architectures
W Rao, A Orailoq, R Karri
2006 43rd ACM/IEEE Design Automation Conference, 723-726, 2006
IC Piracy Prevention via Design Withholding and Entanglement
WR Soroush Khaleghi, Kai Da Zhao
Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 821 - 826, 2015
Toward future systems with nanoscale devices: Overcoming the reliability challenge
W Rao, C Yang, R Karri, A Orailoglu
Computer 44 (2), 46-53, 2011
Logic level fault tolerance approaches targeting nanoelectronics plas
W Rao, A Orailoglu, R Karri
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-5, 2007
Virtual compression through test vector stitching for scan based designs
W Rao, A Orailoglu
2003 Design, Automation and Test in Europe Conference and Exhibition, 104-109, 2003
Fault tolerant approaches to nanoelectronic programmable logic arrays
W Rao, A Orailoglu, R Karri
37th Annual IEEE/IFIP International Conference on Dependable Systems and …, 2007
Defect-tolerant logic mapping on nanoscale crossbar architectures and yield analysis
Y Su, W Rao
2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2009
Nanofabric topologies and reconfiguration algorithms to support dynamically adaptive fault tolerance
W Rao, A Orailoglu, R Karri
24th IEEE VLSI Test Symposium, 6 pp.-221, 2006
Fault tolerant arithmetic with applications in nanotechnology based systems
W Rao, A Orailoglu, R Karri
2004 International Conferce on Test, 472-478, 2004
Selective hardening of nanopla circuits
I Polian, W Rao
2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI …, 2008
Towards fault tolerant parallel prefix adders in nanoelectronic systems
W Rao, A Orailoglu
2008 Design, Automation and Test in Europe, 360-365, 2008
Fault identification in reconfigurable carry lookahead adders targeting nanoelectronic fabrics
W Rao, A Orailoglu, R Karri
Eleventh IEEE European Test Symposium (ETS'06), 63-68, 2006
Fault tolerant nanoelectronic processor architectures
W Rao, A Orailoglu, R Karri
Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation …, 2005
Frugal linear network-based test decompression for drastic test cost reductions
W Rao, A Orailoglu, G Su
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
Architectural-level fault tolerant computation in nanoelectronic processors
W Rao, A Orailoglu, R Karri
2005 International Conference on Computer Design, 533-539, 2005
An integrated framework toward defect-tolerant logic implementation onto nanocrossbars
Y Su, W Rao
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
Hardware obfuscation using strong pufs
S Khaleghi, W Rao
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 321-326, 2018
Towards nanoelectronics processor architectures
W Rao, A Orailoglu, R Karri
Journal of Electronic Testing 23 (2-3), 235-254, 2007
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