| FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256 I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval Microprocessors and Microsystems 37 (6-7), 750-757, 2013 | 39 | 2013 |
| A compact FPGA-based processor for the Secure Hash Algorithm SHA-256 R García, I Algredo-Badillo, M Morales-Sandoval, C Feregrino-Uribe, ... Computers & Electrical Engineering 40 (1), 194-202, 2014 | 32 | 2014 |
| An area/performance trade-off analysis of a GF (2m) multiplier architecture for elliptic curve cryptography M Morales-Sandoval, C Feregrino-Uribe, R Cumplido, I Algredo-Badillo Computers & Electrical Engineering 35 (1), 54-58, 2009 | 31 | 2009 |
| FPGA implementation and performance evaluation of AES-CCM cores for wireless networks I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval 2008 International Conference on Reconfigurable Computing and FPGAs, 421-426, 2008 | 24 | 2008 |
| A reconfigurable GF(2M) elliptic curve cryptographic coprocessor M Morales-Sandoval, C Feregrino-Uribe, R Cumplido, I Algredo-Badillo 2011 VII Southern Conference on Programmable Logic (SPL), 209-214, 2011 | 22 | 2011 |
| Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11 i standard I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval Computers & Electrical Engineering 36 (3), 565-577, 2010 | 22 | 2010 |
| Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture I Algredo-Badillo, C Feregrino-Uribe, R Cumplido International Conference on Computational Science and Its Applications, 456-465, 2006 | 16 | 2006 |
| FPGA Implementation Cost and Performance Evaluation of the IEEE 802.16 e and IEEE 802.11 i Security Architectures Based on AES-CCM I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval 2008 5th International Conference on Electrical Engineering, Computing …, 2008 | 14 | 2008 |
| Compact FPGA hardware architecture for public key encryption in embedded devices L Rodríguez-Flores, M Morales-Sandoval, R Cumplido, C Feregrino-Uribe, ... PloS one 13 (1), e0190939, 2018 | 13 | 2018 |
| Sistema de Navegación Reactiva Difusa para Giros Suaves de Plataformas Móviles Empleando el Kinect-Fuzzy Mobile Reactive Navigation System for Smooth Turns by Using Kinect CC Martínez, IA Badillo, JJA Pimentel, FA Acevedo, LAM Rosales ReCIBE, Revista electrónica de Computación, Informática, Biomédica y …, 2017 | 11 | 2017 |
| Performance analysis of ANFIS in short term wind speed prediction EC Pérez, I Algredo-Badillo, VHG Rodríguez arXiv preprint arXiv:1212.2671, 2012 | 10 | 2012 |
| Design and implementation of a non-pipelined MD5 Hardware architecture using a new functional description I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval IEICE transactions on information and systems 91 (10), 2519-2523, 2008 | 9 | 2008 |
| Karatsuba-Ofman Multiplier with Integrated Modular Reduction for (2) m GF E Cuevas-Farfan, M Morales-Sandoval, A Morales-Reyes, ... Advances in Electrical and Computer Engineering 13 (2), 2013 | 8 | 2013 |
| Throughput and efficiency analysis of unrolled hardware architectures for the sha-512 hash algorithm I Algredo-Badillo, M Morales-Sandoval, C Feregrino-Uribe, R Cumplido 2012 IEEE Computer Society Annual Symposium on VLSI, 63-68, 2012 | 7 | 2012 |
| De la Secuenciación a la Aceleración Hardware de los Programas de Alineación de ADN, una Revisión Integral D Pacheco Bautista, M González Pérez, I Algredo Badillo Revista mexicana de ingeniería biomédica 36 (3), 259-277, 2015 | 6 | 2015 |
| A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m E Cuevas-Farfan, M Morales-Sandoval, R Cumplido, C Feregrino-Uribe, ... 2013 8th International Workshop on Reconfigurable and Communication-Centric …, 2013 | 5 | 2013 |
| Novel Hardware Architecture for implementing the inner loop of the SHA-2 Algorithms I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval 2011 14th Euromicro Conference on Digital System Design, 543-549, 2011 | 5 | 2011 |
| Real time FPGA-ANN architecture for outdoor obstacle detection focused in road safety I Algredo-Badillo, LA Morales-Rosales, CA Hernandez-Gracidas, ... Journal of Intelligent & Fuzzy Systems 36 (5), 4425-4436, 2019 | 4 | 2019 |
| Reconfigurable arithmetic logic unit designed with threshold logic gates A Medina-Santiago, MA Reyes-Barranca, I Algredo-Badillo, AM Cruz, ... IET Circuits, Devices & Systems 13 (1), 21-30, 2018 | 4 | 2018 |
| A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption L Rodriguez-Flores, M Morales-Sandoval, R Cumplido, C Feregrino-Uribe, ... 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2017 | 4 | 2017 |
