| Signature based diagnosis for logic BIST WT Cheng, M Sharma, T Rinderknecht, L Lai, C Hill 2006 IEEE International Test Conference, 1-9, 2006 | 68 | 2006 |
| Built-in self-test of integrated circuits using selectable weighting of test patterns L Lai, WT Cheng, TH Rinderknecht US Patent 7,840,865, 2010 | 64 | 2010 |
| Logic BIST with scan chain segmentation L Lai, JH Patel, T Rinderknecht, WT Cheng 2004 International Conferce on Test, 57-66, 2004 | 34 | 2004 |
| Hardware efficient LBIST with complementary weights L Lai, JH Patel, T Rinderknecht, WT Cheng 2005 International Conference on Computer Design, 479-481, 2005 | 30 | 2005 |
| Detection and diagnosis of static scan cell internal defect R Guo, L Lai, H Yu, WT Cheng 2008 IEEE International Test Conference, 1-10, 2008 | 28 | 2008 |
| Diagnosis and layout aware (DLA) scan chain stitching J Ye, Y Huang, Y Hu, WT Cheng, R Guo, L Lai, TP Tai, X Li, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (3), 466-479, 2014 | 24 | 2014 |
| Two-dimensional scan architecture Y Huang, WT Cheng, R Guo, M Sharma, L Lai US Patent 9,222,978, 2015 | 15 | 2015 |
| Detection and diagnosis of scan cell internal defects R Guo, L Lai, Y Huang, WT Cheng US Patent 9,086,459, 2015 | 12 | 2015 |
| X-tolerant compactor with on-chip registration and signature-based diagnosis J Tyszer, J Rajski, G Mrugalski, N Mukherjee, M Kassab, WT Cheng, ... IEEE Design & Test of Computers 24 (5), 476-485, 2007 | 12 | 2007 |
| Logic BIST using constrained scan cells L Lai, T Rinderknecht, WT Cheng, JH Patel 22nd IEEE VLSI Test Symposium, 2004. Proceedings., 199-205, 2004 | 10 | 2004 |
| GPU-based hybrid parallel logic simulation for scan patterns L Lai, Q Zhang, H Tsai, WT Cheng 2020 IEEE International Test Conference in Asia (ITC-Asia), 118-123, 2020 | 9 | 2020 |
| Programmable scan-based logic built-in self test L Lai, WT Cheng, T Rinderknecht 16th Asian Test Symposium (ATS 2007), 371-377, 2007 | 9 | 2007 |
| Test access architecture for stacked memory and logic dies WT Cheng, R Guo, Y Huang, L Lai, E Racine, M Keim, R Press, J Ye, ... US Patent 9,689,918, 2017 | 8 | 2017 |
| Test architecture for characterizing interconnects in stacked designs WT Cheng, R Guo, Y Huang, L Lai, J Ye, Y Hu US Patent 9,335,376, 2016 | 6 | 2016 |
| Diagnosis-aware scan chain stitching Y Huang, WT Cheng, R Guo, L Lai US Patent 9,015,543, 2015 | 5 | 2015 |
| Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree Y Huang, WT Cheng, TP Tai, L Lai, R Guo, FM Kuo, YS Chen Int'l Symp. on Test and Failure Analysis (ISTFA), 103-111, 2011 | 5 | 2011 |
| GPGPU-based ATPG system: Myth or reality? L Lai, KH Tsai, H Li IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 3 | 2018 |
| Scalable Parallel Static Learning X Lin, L Lai, H Li 2021 IEEE International Test Conference in Asia (ITC-Asia), 1-6, 2021 | 2 | 2021 |
| STDF memory fail datalog standard A Khoche, J Katz, S Landini, K Liao, N Agrawal, G Plowman, S Zuo, L Lai, ... 2009 27th IEEE VLSI Test Symposium, 209-214, 2009 | 2 | 2009 |
| Adaptive Multi-Dimensional Parallel Fault Simulation Framework on Heterogeneous System J Hu, G Dai, L Wang, L Lai, Y Huang, H Yang, Y Wang IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022 | 1 | 2022 |
