High-level synthesis of dynamic data structures: A case study using Vivado HLS F Winterstein, S Bayliss, GA Constantinides 2013 International conference on field-programmable technology (FPT), 362-365, 2013 | 157 | 2013 |
FPGA-based K-means clustering using tree-based data structures F Winterstein, S Bayliss, GA Constantinides 2013 23rd International Conference on Field programmable Logic and …, 2013 | 69 | 2013 |
Offline synthesis of online dependence testing: Parametric loop pipelining for HLS J Liu, S Bayliss, GA Constantinides 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015 | 43 | 2015 |
MATCHUP: Memory abstractions for heap manipulating programs F Winterstein, K Fleming, HJ Yang, S Bayliss, G Constantinides Proceedings of the 2015 ACM/SIGDA International Symposium on Field …, 2015 | 42 | 2015 |
An FPGA implementation of the simplex algorithm S Bayliss, GA Constantinides, W Luk 2006 IEEE international conference on field programmable technology, 49-56, 2006 | 38 | 2006 |
Optimizing SDRAM bandwidth for custom FPGA loop accelerators S Bayliss, GA Constantinides Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012 | 37 | 2012 |
Polyhedral-based dynamic loop pipelining for high-level synthesis J Liu, J Wickerson, S Bayliss, GA Constantinides IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 36 | 2017 |
Datapath synthesis for overclocking: Online arithmetic for latency-accuracy trade-offs K Shi, D Boland, E Stott, S Bayliss, GA Constantinides Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 31 | 2014 |
Survey of domain-specific languages for FPGA computing N Kapre, S Bayliss 2016 26th International Conference on Field Programmable Logic and …, 2016 | 30 | 2016 |
SOAP: structural optimization of arithmetic expressions for high-level synthesis X Gao, S Bayliss, GA Constantinides 2013 International Conference on Field-Programmable Technology (FPT), 112-119, 2013 | 24 | 2013 |
Separation logic-assisted code transformations for efficient high-level synthesis F Winterstein, S Bayliss, GA Constantinides 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014 | 23 | 2014 |
GPU vs FPGA: A comparative analysis for non-standard precision UI Minhas, S Bayliss, GA Constantinides Reconfigurable Computing: Architectures, Tools, and Applications: 10th …, 2014 | 23 | 2014 |
Methodology for designing statically scheduled application-specific SDRAM controllers using constrained local search S Bayliss, GA Constantinides 2009 International Conference on Field-Programmable Technology, 304-307, 2009 | 23 | 2009 |
Vyasa: A high-performance vectorizing compiler for tensor convolutions on the xilinx ai engine P Chatarasi, S Neuendorffer, S Bayliss, K Vissers, V Sarkar 2020 IEEE High Performance Extreme Computing Conference (HPEC), 1-10, 2020 | 16 | 2020 |
Area implications of memory partitioning for high-level synthesis on FPGAs L Gallo, A Cilardo, D Thomas, S Bayliss, GA Constantinides 2014 24th International Conference on Field Programmable Logic and …, 2014 | 14 | 2014 |
Separation logic for high-level synthesis FJ Winterstein, SR Bayliss, GA Constantinides ACM Transactions on Reconfigurable Technology and Systems (TRETS) 9 (2), 1-23, 2015 | 13 | 2015 |
Application specific memory access, reuse and reordering for SDRAM S Bayliss, GA Constantinides International Symposium on Applied Reconfigurable Computing, 41-52, 2011 | 12 | 2011 |
The evolution of domain-specific computing for deep learning S Neuendorffer, AK Khodamoradi, K Denolf, AK Jain, S Bayliss IEEE Circuits and Systems Magazine 21 (2), 75-96, 2021 | 7 | 2021 |
Dataflow graph programming environment for a heterogenous processing system SA Gupta, SR Bayliss, VK Kathail, RD Wittig, PB James-Roxby, A Sastry US Patent 11,204,745, 2021 | 6 | 2021 |
Control and reconfiguration of data flow graphs on heterogeneous computing platform CJ Hsu, SA Gupta, SR Bayliss, PB James-Roxby, RD Wittig, V Kathail US Patent 10,802,807, 2020 | 6 | 2020 |