| Adaptive insertion policies for managing shared caches A Jaleel, W Hasenplaugh, M Qureshi, J Sebot, S Steely Jr, J Emer Proceedings of the 17th international conference on Parallel architectures …, 2008 | 424 | 2008 |
| Method and apparatus for parallel shift right merge of data J Sebot, WW Macy, E Debes, HV Nguyen US Patent 7,272,622, 2007 | 105 | 2007 |
| Fast full search motion estimation with SIMD merge instruction J Sebot, WW Macy, E Debes US Patent 7,685,212, 2010 | 63 | 2010 |
| Improving 3D geometry transformations on a simultaneous multithreaded SIMD processor C Limousin, J Sebot, A Vartanian, N Drach-Temam Proceedings of the 15th International Conference on Supercomputing, 236-245, 2001 | 30 | 2001 |
| Method and apparatus for performing horizontal addition and subtraction WW Macy, E Debes, MJ Buxton, P Roussel, J Sebot, HV Nguyen US Patent 7,395,302, 2008 | 29 | 2008 |
| Post-silicon cpu adaptation made practical using machine learning SJ Tarsa, RBR Chowdhury, J Sebot, G Chinya, J Gaur, ... Proceedings of the 46th International Symposium on Computer Architecture, 14-26, 2019 | 22 | 2019 |
| Memory bandwidth: The true bottleneck of SIMD multimedia performance on a superscalar processor J Sebot, N Drach-Temam Euro-Par 2001 Parallel Processing: 7th International Euro-Par Conference …, 2001 | 21 | 2001 |
| Processor to execute shift right merge instructions J Sebot, WW Macy Jr, EL Debes, HV Nguyen US Patent 10,732,973, 2020 | 20* | 2020 |
| Bitstream buffer manipulation with a SIMD merge instruction YK Chen, WW Macy Jr, M Holliman, EL Debes, MM Yeung, HV Nguyen, ... US Patent 9,182,988, 2015 | 15 | 2015 |
| Hotgauge: A methodology for characterizing advanced hotspots in modern and next generation processors A Hankin, D Werner, M Amiraski, J Sebot, K Vaidyanathan, M Hempstead 2021 IEEE International Symposium on Workload Characterization (IISWC), 163-175, 2021 | 9 | 2021 |
| SIMD extensions: reducing power consumption on a superscalar processor for multimedia applications J Sebot, N Drach Cool Chips IV, 2001 | 9 | 2001 |
| Apparatus and method for determining the number of execution cores to keep active in a processor AN Ananthakrishnan, JF Sebot, JD Schwartz, SH Gunther, EC Samson US Patent 9,037,889, 2015 | 8 | 2015 |
| Architecture optimization for multimedia application exploiting data and thread-level parallelism C Limousin, J Sebot, A Vartanian, N Drach Journal of Systems Architecture 51 (1), 15-27, 2005 | 7 | 2005 |
| A performance evaluation of multimedia kernels using altivec streaming simd extensions J Sebot, N Drach-Temam Sixth International Symposium on High Performance Computer Architecture …, 2000 | 7 | 2000 |
| A parallel algorithm for 3D geometry transformations in opengl J Sébot Julien, A Vartanian, JL Bechennec, N Drach-Temam Euro-Parą99 Parallel Processing: 5th International Euro-Par Conference …, 1999 | 6 | 1999 |
| S., AND EMER, J. 2008. Adaptive insertion policies for managing shared caches A Jaleel, W Hasenplaugh, M QURESHI, J SEBOT, JR STEELY Proceedings of the 2008 International Conference on Parallel Architectures …, 0 | 5 | |
| Impact des extensions SIMD sur les performances d'applications multimedias. La bande passante memoire limite AltiVec J Sebot TSI-Technique et Science Informatiques-RAIRO 21 (2), 183-202, 2002 | 4 | 2002 |
| Digitally coordinated dynamically adaptable clock and voltage supply apparatus and method J Sebot, EA Burton, NA Kurd, J Douglas US Patent 11,537,375, 2022 | 3 | 2022 |
| Mitigating branch prediction and other timing based side channel attacks J Sebot, S Gueron US Patent 8,869,294, 2014 | 3 | 2014 |
| Simd isa extensions: Tradeoff between power consumption and performance on a superscalar processor N Drach, J Sebot Kool Chips Workshop, Micro 33, 2000 | 3 | 2000 |
