Vassilis Paliouras

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Athanasios (Thanos) StouraitisKhalifa University, UAE, and University of Patras, GreeceVerified email at ku.ac.ae
Ioannis KouretasUniversity of PatrasVerified email at upatras.gr
Ahmed MahdiVassilis PaliourasVerified email at ece.upatras.gr
Dimitrios SoudrisProfessor, Electrical & Computer Eng., National Technical Univ. of AthensVerified email at microlab.ntua.gr
Emmanouil KavvousanosPhD Candidate, Electrical & Computer Engineering Department, University of PatrasVerified email at ece.upatras.gr
Dimitris VordonisPhD Candidate at University of PatrasVerified email at upnet.gr
Charis BasetasPhD candidate, National Technical University of AthensVerified email at central.ntua.gr
Giorgos DimitrakopoulosDemocritus University of ThraceVerified email at ee.duth.gr
Michael BirbasAssociate Professor at Dept of Electrical and Computer Engineering of Patras UniversityVerified email at ece.upatras.gr
Ioannis ParaskevakosResearch Software Engineer, Princeton UniversityVerified email at princeton.edu
John CowlesProfessor of Computer Science, University of WyomingVerified email at uwyo.edu
Apostolos FournarisIndustrial Systems Institute, R.C. ATHENAVerified email at isi.gr
Panagiotis VouzisCarnegie Mellon UniversityVerified email at cmu.edu
Alexios BirbasUniversity Of PatrasVerified email at ece.upatras.gr
Konstantinos N. VoudourisProfessor of Wireless Communications, University of West Attica, Athens, GreeceVerified email at uniwa.gr
Grigorios KalivasAssociate Professor of Electrical adn Computer Engineering, Un. of PatrasVerified email at ece.upatras.gr
Ioannis (John) KorinthiosLecturer, University of ThessalyVerified email at dib.uth.gr
Rodoula MakriInstitute of Communications & Computer Systems - National Technical University of AthensVerified email at esd.ece.ntua.gr
Evangelos HaleplidisUniversity of Piraeus - Department of Digital SystemsVerified email at unipi.gr
Odysseas KoufopavlouProfessor of Electrical and Computer Engineering, University of PatrasVerified email at ece.upatras.gr

Vassilis Paliouras

Professor, Department of Electrical and Computer Engineering, University of Patras

Verified email at ece.upatras.gr - Homepage

integrated systems design and implementation of signal processing systems error correction computer arithmetic low power


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
Considering the alternatives in low-power design T Stouraitis, V Paliouras IEEE Circuits and Devices Magazine 17 (4), 22-29, 2001	120	2001
Simplified hardware implementation of the softmax activation function I Kouretas, V Paliouras 2019 8th international conference on modern circuits and systems …, 2019	107	2019
Low-power properties of the logarithmic number system V Paliouras, T Stouraitis Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, 229-236, 2001	95	2001
Low-power logarithmic number system addition/subtraction and their impact on digital filters I Kouretas, C Basetas, V Paliouras IEEE Transactions on Computers 62 (11), 2196-2209, 2012	57	2012
A reconfigurable LDPC decoder optimized for 802.11 n/ac applications I Tsatsaragkos, V Paliouras IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (1), 182-195, 2017	43	2017
Multifunction architectures for RNS processors V Paliouras, T Stouraitis IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1999	41	1999
A VLSI design methodology for RNS full adder-based inner product architectures DJ Soudris, V Paliouras, T Stouraitis, CE Goutis IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1997	39	1997
A low-complexity combinatorial RNS multiplier V Paliouras, K Karagianni, T Stouraitis IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001	38	2001
A floating-point processor for fast and accurate sine/cosine evaluation V Paliouras, K Karagianni, T Stouraitis IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2000	37	2000
Hardware implementation of a softmax-like function for deep learning I Kouretas, V Paliouras Technologies 8 (3), 46, 2020	36	2020
Logarithmic number system for low-power arithmetic V Paliouras, T Stouraitis Integrated Circuit Design: Power and Timing Modeling, Optimization and …, 2000	34	2000
A novel algorithm for accurate logarithmic number system subtraction V Paliouras, T Stouraitis 1996 IEEE International Symposium on Circuits and Systems. Circuits and …, 1996	34	1996
A low complexity-high throughput QC-LDPC encoder A Mahdi, V Paliouras IEEE transactions on signal processing 62 (10), 2696-2708, 2014	30	2014
Novel high-radix residue number system architectures V Paliouras, T Stouraitis IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2000	30	2000
Approximate algorithms for identifying minima on min-sum LDPC decoders and their hardware implementation I Tsatsaragkos, V Paliouras IEEE Transactions on Circuits and Systems II: Express Briefs 62 (8), 766-770, 2015	29	2015
LDPC encoding and decoding techniques I Tsatsaragkos, A Mahdi, N Kanistras, V Paliouras US Patent 8,739,001, 2014	29	2014
Novel high-radix residue number system multipliers and adders V Paliouras, T Stouraitis 1999 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 451-454, 1999	28	1999
A multirate fully parallel LDPC encoder for the IEEE 802.11 n/ac/ax QC-LDPC codes based on reduced complexity XOR trees A Mahdi, N Kanistras, V Paliouras IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (1), 51-64, 2020	26	2020
A low-power termination criterion for iterative LDPC code decoders G Glikiotis, V Paliouras IEEE Workshop on Signal Processing Systems Design and Implementation, 2005 …, 2005	25	2005
A low-complexity high-radix RNS multiplier I Kouretas, V Paliouras IEEE Transactions on Circuits and Systems I: Regular Papers 56 (11), 2449-2462, 2009	24	2009

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