Dimitrios Balobas
Dimitrios Balobas
Verified email at csd.auth.gr
Cited by
Cited by
Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders
D Balobas, N Konofaos
IEEE Transactions on Circuits and Systems II: Express Briefs 64 (2), 175-180, 2017
Low power high performance CMOS 5-2 compressor with 58 transistors
D Balobas, N Konofaos
Electronics Letters, 2018
Design and simulation of 6T SRAM cell architectures in 32nm technology
G Apostolidis, D Balobas, N Konofaos
Journal of Engineering Science and Technology Review 9 (5), 145-149, 2016
Low-power, high-performance 64-bit CMOS priority encoder using static-dynamic parallel architecture
D Balobas, N Konofaos
Modern Circuits and Systems Technologies (MOCAST), 2016 5th International …, 2016
High-performance and energy-efficient 256-bit CMOS Priority Encoder
D Balobas, N Konofaos
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 122-127, 2017
Ultra-low-power and compact 8-bit CMOS priority encoder
D Balobas, N Konofaos
International Journal of Electronics Letters 5 (3), 272-278, 2017
Design and evaluation of 6T SRAM layout designs at modern nanoscale CMOS processes
D Balobas, N Konofaos
4th International Conference on Modern Circuits and Systems Technologies …, 2015
A VHDL implementation of the Hummingbird cryptographic algorithm
S Mammou, D Balobas, N Konofaos
4th Panhellenic Conference on Electronics and Telecommunications, 1-4, 2017
High-performance and energy-efficient 64-bit incrementer/decrementer using Multiple-Output Monotonic CMOS
D Balobas, N Konofaos
Integration the VLSI Journal, 2018
Design and Simulation of Mixed Logic 2 - to - 4 Line Decoders at 32 nm CMOS technology
D Balobas, N Konofaos
6th Micro&Nano Conference on Micro - Nanoelectronics, Nanotechnologies and …, 2015
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