Shin-haeng Kang
Shin-haeng Kang
Staff Researcher, Samsung Electronics.
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα iris.snu.ac.kr
Τίτλος
Παρατίθεται από
Παρατίθεται από
Έτος
Scenario-based design flow for mapping streaming applications onto on-chip many-core systems
L Schor, I Bacivarov, D Rai, H Yang, SH Kang, L Thiele
Proceedings of the 2012 international conference on Compilers, architectures …, 2012
1382012
Multi-objective mapping optimization via problem decomposition for many-core systems
SH Kang, H Yang, L Schor, I Bacivarov, S Ha, L Thiele
2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 28-37, 2012
422012
Static mapping of mixed-critical applications for fault-tolerant MPSoCs
S Kang, H Yang, S Kim, I Bacivarov, S Ha, L Thiele
Proceedings of the 51st annual design automation conference, 1-6, 2014
392014
Dynamic behavior specification and dynamic mapping for real-time embedded systems: Hopes approach
H Jung, C Lee, SH Kang, S Kim, H Oh, S Ha
ACM Transactions on Embedded Computing Systems (TECS) 13 (4s), 1-26, 2014
372014
Reliability-aware mapping optimization of multi-core systems with mixed-criticality
SH Kang, H Yang, S Kim, I Bacivarov, S Ha, L Thiele
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
252014
An ILP-based worst-case performance analysis technique for distributed real-time embedded systems
J Kim, H Oh, H Ha, SH Kang, J Choi, S Ha
2012 IEEE 33rd Real-Time Systems Symposium, 363-372, 2012
172012
TQSIM: A fast cycle-approximate processor simulator based on QEMU
S Kang, D Yoo, S Ha
Journal of Systems Architecture 66, 33-47, 2016
152016
Real-time co-scheduling of multiple dataflow graphs on multi-processor systems
S Kang, D Kang, H Yang, S Ha
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
82016
Optimal checkpoint selection with dual-modular redundancy hardening
SH Kang, H Park, S Kim, H Oh, S Ha
IEEE Transactions on Computers 64 (7), 2036-2048, 2014
72014
25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2 TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications
YC Kwon, SH Lee, J Lee, SH Kwon, JM Ryu, JP Son, O Seongil, HS Yu, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 350-352, 2021
62021
Fast parallel simulation of a manycore architecture with a flit-level on-chip network model
S Kang, J Kang, S Ha
Proceedings of the 18th International Conference on Embedded Computer …, 2018
12018
Near-Memory Processing in Action: Accelerating Personalized Recommendation with AxDIMM
L Ke, X Zhang, J So, JG Lee, SH Kang, S Lee, S Han, Y Cho, JH Kim, ...
IEEE Micro, 2021
2021
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology: Industrial Product
S Lee, S Kang, J Lee, H Kim, E Lee, S Seo, H Yoon, S Lee, K Lim, H Shin, ...
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
2021
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