Dr. Sudarshan Tiwari
Dr. Sudarshan Tiwari
Director National Institute of Technology, Raipur, India
No verified email
Title
Cited by
Cited by
Year
Energy efficient clustering algorithms in wireless sensor networks: A survey
V Kumar, S Jain, S Tiwari
International Journal of Computer Science Issues (IJCSI) 8 (5), 259, 2011
2812011
Performance evaluation of conventional and wavelet based OFDM system
MK Gupta, S Tiwari
AEU-International Journal of Electronics and Communications 67 (4), 348-354, 2013
832013
Analysis and design of optimum interleaver for iterative receivers in IDMA scheme
M Shukla, VK Srivastava, S Tiwari
Wireless Communications and Mobile Computing 9 (10), 1312-1317, 2009
622009
Optimal number of clusters in wireless sensor networks: a FCM approach
AS Raghuvanshi, S Tiwari, R Tripathi, N Kishor
International Journal of Sensor Networks 12 (1), 16-24, 2012
592012
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design
S Wairya, RK Nagaria, S Tiwari
International Journal of VLSI Design & Communication Systems 3 (2), 221, 2012
542012
Design analysis of XOR (4T) based low voltage CMOS full adder circuit
S Wairya, G Singh, RK Nagaria, S Tiwari
2011 Nirma University International Conference on Engineering, 1-7, 2011
532011
Analysis and design of Tree Based Interleaver for multiuser receivers in IDMA scheme
M Shukla, VK Srivastava, S Tiwari
2008 16th IEEE International Conference on Networks, 1-4, 2008
522008
New design methodologies for high speed low power XOR-XNOR circuits
SS Mishra, S Wairya, RK Nagaria, S Tiwari
World Academy of Science, Engineering and Technology 55, 200-206, 2009
502009
Prevalence of psychiatric morbidity amongst the community dwelling rural older adults in northern India
SC Tiwari, G Srivastava, RK Tripathi, NM Pandey, GG Agarwal, S Pandey, ...
The Indian journal of medical research 138 (4), 504, 2013
482013
Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design
S Wairya, RK Nagaria, S Tiwari
VLSI Design 2012, 2012
482012
Routing in IPv6 over low-power wireless personal area networks (6LoWPAN): A survey
V Kumar, S Tiwari
Journal of Computer Networks and Communications 2012, 2012
442012
New design methodologies for high-speed mixed-mode cmos full adder circuits
S Wairya, RK Nagaria, S Tiwari
International Journal of VLSI design & Communication Systems (VLSICS) Vol 2, 2011
412011
Investigation of ionospheric irregularities and scintillation using TEC at high latitude
R Tiwari, HJ Strangeways, S Tiwari, A Ahmed
Advances in Space Research 52 (6), 1111-1124, 2013
402013
A new mixed gate diffusion input full adder topology for high speed low power digital circuits
AK Agrawal, S Wairya, RK Nagaria, S Tiwari
World Applied Science Journal 7, 138-144, 2009
322009
Cluster size optimisation with Tunable Elfes sensing model for single and multi-hop wireless sensor networks
V Kumar, SB Dhok, R Tripathi, S Tiwari
International Journal of Electronics 104 (2), 312-327, 2017
232017
Performance evaluation and comparison of aodv and dsr under adversarial environment
R Agrawal, R Tripathi, S Tiwari
2011 International Conference on Computational Intelligence and …, 2011
232011
Performance of routing protocols for beacon-enabled IEEE 802.15. 4 WSNs with different duty cycle
V Kumar, S Tiwari
2011 International Conference on Devices and Communications (ICDeCom), 1-5, 2011
222011
Ultra low voltage high speed 1-bit CMOS adder
S Wairya, H Pandey, RK Nagaria, S Tiwari
2010 International Conference on Power, Control and Embedded Systems, 1-6, 2010
222010
A review study of hierarchical clustering algorithms for wireless sensor networks
V Kumar, SB Dhok, R Tripathi, S Tiwari
International Journal of Computer Science Issues (IJCSI) 11 (3), 92, 2014
212014
Channel estimation for wavelet based OFDM system
MK Gupta, S Shrivastava, AS Raghuvanshi, S Tiwari
2011 International conference on devices and communications (ICDeCom), 1-4, 2011
212011
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Articles 1–20