| An efficient seeds selection method for LFSR-based test-per-clock BIST E Kalligeros, X Kavousianos, D Bakalis, D Nikolos Proceedings International Symposium on Quality Electronic Design, 261-266, 2002 | 29 | 2002 |
| Efficient partial scan cell gating for low-power scan-based testing X Kavousianos, D Bakalis, D Nikolos ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (2 …, 2009 | 28 | 2009 |
| On-the-fly reseeding: A new reseeding technique for test-per-clock BIST E Kalligeros, X Kavousianos, D Bakalis, D Nikolos Journal of Electronic Testing 18, 315-332, 2002 | 25 | 2002 |
| On the design of self-testing checkers for modified Berger codes SJ Piestrak, D Bakalis, X Kavousianos Proceedings Seventh International On-Line Testing Workshop, 153-157, 2001 | 25 | 2001 |
| Scan cell ordering for low power BIST M Bellos, D Bakalis, D Nikolos IEEE Computer Society Annual Symposium on VLSI, 281-284, 2004 | 22 | 2004 |
| New reseeding technique for LFSR-based test pattern generation E Kalligeros, X Kavousianos, D Bakalis, D Nikolos Proceedings Seventh International On-Line Testing Workshop, 80-86, 2001 | 22 | 2001 |
| On the Design of Modulo 2 n ±1 Subtractors and Adders/Subtractors E Vassalos, D Bakalis, HT Vergos Circuits, Systems, and Signal Processing 30, 1445-1461, 2011 | 21 | 2011 |
| RNS assisted image filtering and edge detection E Vassalos, D Bakalis, HT Vergos 2013 18th International Conference on Digital Signal Processing (DSP), 1-6, 2013 | 19 | 2013 |
| An efficient test vector ordering method for low power testing X Kavousianos, D Bakalis, M Bellos, D Nikolos IEEE Computer Society Annual Symposium on VLSI, 285-288, 2004 | 19 | 2004 |
| Fast modulo 2n+ 1 multi-operand adders and residue generators HT Vergos, D Bakalis, C Efstathiou Integration, the VLSI Journal 43 (1), 42-48, 2010 | 18 | 2010 |
| Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register D Bakalis, D Nikolos, X Kavousianos Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000 | 17 | 2000 |
| On the use of diminished-1 adders for weighted modulo 2n+ 1 arithmetic components HT Vergos, D Bakalis 2008 11th EUROMICRO Conference on Digital System Design Architectures …, 2008 | 16 | 2008 |
| Efficient modulo 2n±1 squarers D Bakalis, HT Vergos, A Spyrou Integration 44 (3), 163-174, 2011 | 14 | 2011 |
| On implementing efficient modulo 2n+ 1 arithmetic components HT Vergos, D Bakalis Journal of Circuits, Systems, and Computers 19 (05), 911-930, 2010 | 14 | 2010 |
| A core generator for arithmetic cores and testing structures with a network interface D Bakalis, KD Adaos, D Lymperopoulos, M Bellos, HT Vergos, GP Alexiou, ... Journal of Systems Architecture 52 (1), 1-12, 2006 | 13 | 2006 |
| Low power dissipation in BIST schemes for modified booth multipliers D Bakalis, HT Vergos, D Nikolos, X Kavousianos, GP Alexiou Defect and Fault Tolerance in VLSI Systems, 1999. DFT'99. International …, 1999 | 13 | 1999 |
| Low power BIST for wallace tree-based multipliers D Bakalis, E Kalligeros, D Nikolos, HT Vergos, G Alexiou Proceedings IEEE 2000 First International Symposium on Quality Electronic …, 2000 | 11 | 2000 |
| On low power BIST for carry save array multipliers D Bakalis, D Nikolos Proceedings of the 5th International On-Line Testing Workshop, 86-90, 1999 | 11 | 1999 |
| Modulo 2^ n+ 1 Arithmetic Units with Embedded Diminished-to-Normal Conversion E Vassalos, D Bakalis, HT Vergos 2011 14th Euromicro Conference on Digital System Design, 468-475, 2011 | 10 | 2011 |
| Shifter circuits for {2n+1, 2n, 2n−1} RNS D Bakalis, HT Vergos Electronics letters 1 (45), 27-29, 2009 | 10 | 2009 |
Haridimos T. VergosProfessor, Computer Engineering & Informatics Dept, University of PatrasΗ διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα ceid.upatras.gr
