Παρακολούθηση
Dimitris Bakalis
Dimitris Bakalis
Assistant Professor, University of Patras
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα physics.upatras.gr
Τίτλος
Παρατίθεται από
Παρατίθεται από
Έτος
An efficient seeds selection method for LFSR-based test-per-clock BIST
E Kalligeros, X Kavousianos, D Bakalis, D Nikolos
Proceedings International Symposium on Quality Electronic Design, 261-266, 2002
292002
Efficient partial scan cell gating for low-power scan-based testing
X Kavousianos, D Bakalis, D Nikolos
ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (2 …, 2009
272009
On the design of self-testing checkers for modified Berger codes
SJ Piestrak, D Bakalis, X Kavousianos
Proceedings Seventh International On-Line Testing Workshop, 153-157, 2001
262001
On-the-fly reseeding: A new reseeding technique for test-per-clock BIST
E Kalligeros, X Kavousianos, D Bakalis, D Nikolos
Journal of Electronic Testing 18 (3), 315-332, 2002
252002
New reseeding technique for LFSR-based test pattern generation
E Kalligeros, X Kavousianos, D Bakalis, D Nikolos
Proceedings Seventh International On-Line Testing Workshop, 80-86, 2001
222001
Scan cell ordering for low power BIST
M Bellos, D Bakalis, D Nikolos
IEEE Computer Society Annual Symposium on VLSI, 281-284, 2004
212004
RNS assisted image filtering and edge detection
E Vassalos, D Bakalis, HT Vergos
2013 18th International Conference on Digital Signal Processing (DSP), 1-6, 2013
192013
Fast modulo 2n+ 1 multi-operand adders and residue generators
HT Vergos, D Bakalis, C Efstathiou
Integration, the VLSI Journal 43 (1), 42-48, 2010
182010
On the use of diminished-1 adders for weighted modulo 2n+ 1 arithmetic components
HT Vergos, D Bakalis
2008 11th EUROMICRO Conference on Digital System Design Architectures …, 2008
172008
Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register
D Bakalis, D Nikolos, X Kavousianos
Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000
172000
An efficient test vector ordering method for low power testing
X Kavousianos, D Bakalis, M Bellos, D Nikolos
IEEE Computer Society Annual Symposium on VLSI, 285-288, 2004
162004
On the design of modulo 2 n±1 subtractors and adders/subtractors
E Vassalos, D Bakalis, HT Vergos
Circuits, Systems, and Signal Processing 30 (6), 1445-1461, 2011
152011
Low power dissipation in BIST schemes for modified booth multipliers
D Bakalis, HT Vergos, D Nikolos, X Kavousianos, GP Alexiou
Defect and Fault Tolerance in VLSI Systems, 1999. DFT'99. International …, 1999
141999
On implementing efficient modulo 2n+ 1 arithmetic components
HT Vergos, D Bakalis
Journal of Circuits, Systems, and Computers 19 (05), 911-930, 2010
132010
A core generator for arithmetic cores and testing structures with a network interface
D Bakalis, KD Adaos, D Lymperopoulos, M Bellos, HT Vergos, GP Alexiou, ...
Journal of Systems Architecture 52 (1), 1-12, 2006
132006
Efficient modulo 2n±1 squarers
D Bakalis, HT Vergos, A Spyrou
Integration 44 (3), 163-174, 2011
112011
Low power BIST for wallace tree-based multipliers
D Bakalis, E Kalligeros, D Nikolos, HT Vergos, G Alexiou
Proceedings IEEE 2000 First International Symposium on Quality Electronic …, 2000
112000
On low power BIST for carry save array multipliers
D Bakalis, D Nikolos
Proceedings of the 5th International On-Line Testing Workshop, 86-90, 1999
111999
Modulo 2^ n+ 1 Arithmetic Units with Embedded Diminished-to-Normal Conversion
E Vassalos, D Bakalis, HT Vergos
2011 14th Euromicro Conference on Digital System Design, 468-475, 2011
102011
Shifter circuits for {2n+1, 2n, 2n−1} RNS
D Bakalis, HT Vergos
Electronics letters 1 (45), 27-29, 2009
102009
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